Lesson24Memory电子技术专业英语教程.ppt

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1、2023/11/8,1,Unit10 Computer Program Design,Lesson 24 Memory电子技术专业英语教程冯新宇 主编电子工业出版社,2023/11/8,2,Lesson 24 Memory,BackgroundsText tour Language in useVocabulary Structure Reading/writing techniques,2023/11/8,3,Terminology RAM随机存储器DRAM动态随机存储器DDR（Double Data Rate）双倍数据数率prefetching预取指令，预取数double transiti

2、on clocking 双倍传输时钟DIMM双直列内存模块；双线内存模块operating system操作系统peak bandwidth峰值带宽,Backgrounds,2023/11/8,4,Text tour,Outline-IntroductionDDR1 DDR2 DDR3,2023/11/8,5,Introduction,Processors use system memory to temporarily store the operating system,mission-critical applications,and the data they use and mani

3、pulate.Therefore,the performance of the applications and reliability of the data are intrinsically tied to the speed and bandwidth of the system memory.Over the years,these factors have driven the evolution of system memory from asynchronous DRAM technologies,such as Fast Page Mode(FPM)memory and Ex

4、tended Data Output(EDO)memory,to high-bandwidth synchronous DRAM(SDRAM)technologies.Yet,system memory bandwidth has not kept pace with improvements in processor performance,thus creating a“performance gap”.Processor performance,which is often equated to the number of transistors in a chip,doubles ev

5、ery couple of years.On the other hand,memory bandwidth doubles roughly every three years.Therefore,if processor and memory performance continue to increase at these rates,the performance gap between them will widen.,2023/11/8,6,Introduction,Why is the processor-memory performance gap important?The p

6、rocessor is forced to idle while it waits for data from system memory.Thus,the performance gap prevents many applications from effectively using the full computing power of modern processors.In an attempt to narrow the performance gap,the industry vigorously pursues the development of new memory tec

7、hnologies.HP works with Joint Electronic Device Engineering Council(JEDEC)memory vendors and chipset developers during memory technology development to ensure that new memory products fulfill customer needs in regards to reliability,cost,and backward compatibility.,2023/11/8,7,DDR1,To develop the fi

8、rst generation of DDR SDRAM(DDR-1),designers made enhancements to the SDRAM core to increase the data rate.These enhancements include prefetching,double transition clocking,strobe-based data bus,and SSTL1_2 low voltage signaling.At 400 MHz,DDR increases memory bandwidth to 3.2 GB/s,this is 400 perce

9、nt more than original SDRAM.,2023/11/8,8,DDR1,In SDRAM,one bit per clock cycle is transferred from the memory cell array to the input/output(I/O)buffer or data queue(DQ).The I/O buffer releases one bit to the bus per pin and clock cycle(on the rising edge of the clock signal).To double the data rate

10、,DDR SDRAM uses a technique called prefetching to transfer two bits from the memory cell array to the I/O buffer in two separate pipelines.Then the I/O buffer releases the bits in the order of the queue on the same output line.This is known as 2n-prefetch architecture because the two data bits are f

11、etched from the memory cell array before they are released to the bus in a time multiplexed manner.,2023/11/8,9,DDR1,Standard DRAM transfers one data bit to the bus on the rising edge of the bus clock signal,while DDR-1 uses both the rising and falling edges of the clock to trigger the data transfer

12、 to the bus.This technique,known as double transition clocking,delivers twice the bandwidth of SDRAM without increasing the clock frequency.DDR-1 has theoretical peak data transfer rates of 1.6 and 2.1 GB/s at clock frequencies of 100 MHz and 133 MHz,respectively.,2023/11/8,10,Another difference bet

13、ween SDRAM and DDR-1 is the signaling technology.Instead of using a 3.3V operating voltage,DDR-1 uses a 2.5V signaling specification known as Stub Series-Terminated Logic_2(SSTL_2).This low-voltage signaling results in lower power consumption and improved heat dissipation.Appearance in Figure 24-1.,

14、Figure 24-1 DDR1 MEMORY,2023/11/8,11,DDR2,DDR-2 SDRAM is the second generation of DDR SDRAM.It offers data rates of up to 6.4 GB/s,lower power consumption,and improvements in packaging.At 400 MHz and 800 Mb/s,DDR-2 increases memory bandwidth to 6.4 GB/s,which is 800 percent more than original SDRAM.

15、DDR-2 SDRAM achieves this higher level of performance and lower power consumption through faster clocks,1.8V operation and signaling,and simplification of the command set.The 240-pin connector on DDR-2 is needed to accommodate differential strobes signals.Appearance in Figure 24-2.,2023/11/8,12,Figu

16、re 24-2 DDR2 MEMORY,2023/11/8,13,DDR3,DDR-3,the third-generation of DDR SDRAM technology,will make further improvements in bandwidth and power consumption.Manufacturers of DDR-3 will initially use 90 nm fabrication technology and move toward 70 nm as production volumes increase.DDR-3 will operate at

17、 clock rates from 400 MHz to 800 MHz with theoretical peak bandwidths ranging from 6.40 GB/s to 12.8 GB/s.DDR-3 is expected to reduce power consumption by up to 30%compared to a DDR-2 DIMM operating at the same speed.DDR-3 DIMMs are expected to use the same 240-pin connector as DDR2 DIMMs,but the ke

18、y notch will be in a different position.,2023/11/8,14,Summary of DDR SDRAM technologies,2023/11/8,15,Vocabulary reliability enhancement convention StructureReading/writing techniques,Language in use,2023/11/8,16,Vocabulary,2023/11/8,17,reliability in dictionary,analysis of structure reliability 结构可靠

19、度分析 Introduction to Reliability Technology 可靠性技术导论 mathematical theory of reliability 可靠性数学理论 reliability of computer system 计算机系统可靠性 reliability of electrical apparatus 电器可靠性,2023/11/8,18,reliability in text,Therefore,the performance of the applications and reliability of the data are intrinsically

20、 tied to the speed and bandwidth of the system memory.因此，应用程序的性能和数据的可靠性本质上依赖于系统内存的速度和带宽。,2023/11/8,19,enhancement in dictionary,enhancement of fishery resources 水产资源增殖 enhancement factor of mass transfer 传质增强因子 Enhancement of the Financial Infrastructure 改善金融基础设施。enhancement/depletion MOS integrated

21、 circuit 增强型与耗尽型金属-氧化物-半导体集成电路 intensifying by augmentation and enhancement.通过增加和改进而强化的。,2023/11/8,20,enhancement in text,To develop the first generation of DDR SDRAM(DDR-1),designers made enhancements to the SDRAM core to increase the data rate.为了开发DDR SDRAM的第一代（DDR-1），设计人员对SDRAM核采取了增强措施以增加数据传输率。,2

22、023/11/8,21,convention in dictionary,convention on consular relations 领事关系公约 convention on diplomatic relations 外交关系公约 Specific Conventional Weapons Convention 禁止或限制使用特定常规武器公约 Straits Convention of London 伦敦海峡公约 International Convention for Safe Containers 国际集装箱安全公约,2023/11/8,22,convention in text,O

23、riginally,the module naming convention for DDR-SDRAM was based on the effective clock rate of the data transfer:PC200 for DDR SDRAM that operates at 100 MHz;PC266 for 133 MHz;and so forth.最初，DDR-SDRAM的命名约定基于有效时钟数据传输速率：PC200的内存工作频率为100MHz；PC266为133 MHz等等。,2023/11/8,23,convention in use,the National Convention 法【史】国民议会（1792-1795）英【史】宪章党员大会 美（政党决定总统候选人的）全国代表大会 convention money(两国以上协定发行的)同本位货币,2023/11/8,24,Structure,2023/11/8,25,Reading/Writing techniques,