计算机专业英语Chapter.ppt

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1、Computer English,Chapter 2 Basic Organization of Computers,Key points:useful terms and basic organization of computersDifficult points:describing the basic organization of computers,Requirements:,Terms of computer hardwareBasic Organization of computers and their functions 掌握专业词汇的构成规律，特别是常用词缀及复合词的构成

2、,New Words&Expressions:subsystem n.子系统operation n.操作，运算，执行命令(计)microprocessor n.计微处理器ystem buses 系统总线sequence n.时序,序列fetch vt.取数，取指令decode vt.解码,译解instruction n.指令,2.1 Introduction,Abbreviations:CPU(Central Processing Unit)中央处理器 I/O(Input/Output)输入输出(设备),Fig.2-1 Generic computer organization,2.1 Int

3、roduction,Most computer systems,from the embedded controllers found in automobiles and consumer appliances to personal computers and mainframes,have the same basic organization.This organization has three main components:the CPU,the memory subsystem,and the I/O subsystem.The generic organization of

4、these components is shown in Figure 2-1.大多数计算机系统，从汽车和日用电器中的嵌入式控制器到个人计算机和大型主机，都具有相同的基本组成。其基本组成包括三个主要部件：CPU、存储器子系统和I/O子系统。这些部件的一般组成如图2-1所示。,2.1 Introduction,2.1 Introduction,In this chapter,we first describe the system buses used to connect the components in the computer system.Then we examine the ins

5、truction cycle,the sequence of operations that occurs within the computer as it fetches,decodes,and executes an instruction.本章我们首先讲述计算机系统中用来连接计算机各部件的系统总线。然后再来考察指令周期，以及计算机在读取、解码和执行一条指令时所发生的操作顺序。,New Words&Expressions:pins n.插脚,管脚address bus 地址总线uppermost adj.最高的；adv.在最上control bus 控制总线data bus 数据总线vi

6、a prep.经,通过,经由multibit 多位bidirectional 双向的unidirectional 单向的hierarchy n.层次，层级I/O bus 输入输出总线local bus n.局域总线,2.2 System Buses,Physically,a bus is a set of wires.The components of the computer are connected to the buses.To send information from one component to another,the source component outputs dat

7、a onto the bus.The destination component then inputs this data from the bus.As the complexity of a computer system increases,it becomes more efficient(in terms of minimizing connections)at using buses rather than direct connections between every pair of devices.Buses use less space on a circuit boar

8、d and require less power than a large number of direct connections.They also require fewer pins on the chip or chips that comprise the CPU.从物理上来说，总线就是一组导线。计算机的部件就是连在总线上的。为了将信息从一个部件传到另一个部件，源部件先将数据输出到总线上，然后目标部件再从总线上接受这些数据。随着计算机系统复杂性的不断增长，使用总线比每个设备对之间直接连接要有效得多（就减少连接数量而言）。与大量的直接连接相比，总线使用较少的电路板空间，耗能更少，并且

9、在芯片或组成CPU的芯片组上需要较少的引脚。,2.2 System Buses,The system shown in Figure 2-1 has three buses.The uppermost bus in this figure is the address bus.When the CPU reads data or instructions from or writes data to memory,it must specify the address of the memory location it wishes to access.It outputs this addr

10、ess to the address bus;memory inputs this address from the address bus and use it to access the proper memory location.Each I/O devices,such as a keyboard,monitor,or disk drive,has a unique address as well.When accessing an I/O device,the CPU places the address of the device on the address bus.Each

11、device can read the address off of the bus and determine whether it is the device being accessed by the CPU.Unlike the other buses,the address bus always receives data from the CPU;the CPU never reads the address bus.图2-1所示的系统包括三组总线。最上面的是地址总线。当CPU从存储器读取数据或指令，或写数据到存储器时，它必须指明将要访问的存储器单元地址。CPU将地址输出到地址总线

12、上，而存储器从地址总线上读取地址，并且用它来访问正确的存储单元。每个I/O设备，比如键盘、显示器或者磁盘，同样都有一个唯一的地址。当访问某个I/O设备时，CPU将此设备的地址放到地址总线上。每一个设备均从总线上读取地址并且判断自己是否就是CPU正要访问的设备。与其他总线不同，地址总线总是从CPU上接收信息，而CPU从不读取地址总线。,2.2 System Buses,Data is transferred via the data bus.When the CPU fetches data from memory,it first outputs the memory address on i

13、ts address bus.Then memory outputs the data onto the data bus;the CPU can then read the data from the data bus.When writing data to memory,the CPU first outputs the address onto the address bus,then outputs the data onto the data bus.Memory then reads and stores the data at the proper location.The p

14、rocesses for reading data from and writing data to the I/O devices are similar.数据是通过数据总线传送的。当CPU从存储器中取数据时，它首先把存储器地址输出到地址总线上，然后存储器将数据输出到数据总线上，这样CPU就可以从数据总线上读取数据了。当CPU向存储器中写数据时，它首先将地址输出到地址总线上，然后把数据输出到数据总线上，这样存储器就可以从数据总线上读取数据并将它存储到正确的单元中。对I/O设备读写数据的过程与此类似。,2.2 System Buses,The control bus is different

15、from the other two buses.The address bus consists of n lines,which combine to transmit one n-bit address value.Similarly,the lines of the data bus work together to transmit a single multibit value.In contrast,the control bus is a collection of individual control signals.These signals indicate whethe

16、r data is to be read into or written out of the CPU,whether the CPU is accessing memory or an I/O device,and whether the I/O device or memory is ready to transfer data.Although this bus is shown as bidirectional in Figure 2-1,it is really a collection of(mostly)unidirectional signals.Most of these s

17、ignals are output from the CPU to the memory and I/O subsystems,although a few are output by these subsystems to the CPU.We examine these signals in more detail when we look at the instruction cycle and the subsystem interface.控制总线与以上两种总线都不相同。地址总线由n根线构成，n根线联合传送一个n位的地址值。类似地，数据总线的各条线合起来传输一个单独的多位值。相反，控

18、制总线是单根控制信号的集合。这些信号用来指示数据是要读入CPU还是要从CPU写出，CPU是要访问存储器还是要访问I/O设备，是I/O设备还是存储器已就绪要传送数据等等。虽然图2-1所示的控制总线看起来是双向的，但它实际上（主要）是单向（大多数都是）信号的集合。大多数信号是从CPU输出到存储器与I/O子系统的，只有少数是从这些子系统输出到CPU的。在介绍指令周期和子系统接口时，我们将详细地讨论这些信号。,2.2 System Buses,A system may have a hierarchy of buses.For example,it may use its address,data,a

19、nd control buses to access memory,and an I/O controller.The I/O controller,in turn,may access all I/O devices using a second bus,often called an I/O bus or a local bus.一个系统可能具有分层次的总线。例如，它可能使用地址、数据和控制总线来访问存储器和I/O控制器。I/O控制器可能依次使用第二级总线来访问所有的I/O设备，第二级总线通常称为I/O总线或者局部总线。,2.2 System Buses,New Words&Express

20、ions:instruction cycle 指令周期memory map n.计内存register n.寄存器port n.端口timing n.定时；时序；时间选择synchronize vt.使.同步assert vt.主张，发出deassert vt.撤销trigger vt.引发,引起,触发map v.映射,2.3 Instruction Cycle,The instruction cycle is the procedure a microprocessor goes through to process an instruction.First the microprocess

21、or fetches,or reads,the instruction from memory.Then it decodes the instruction,determining which instruction it has fetched.Finally,it performs the operations necessary to execute the instruction.(Some people also include an additional element in the instruction cycle to store results.Here,we inclu

22、de that operation as part of the execute function.)Each of these functions-fetch,decode,and execute-consists of a sequence of one or more operations.指令周期是微处理器完成一条指令处理的步骤。首先，微处理器从存储器读取指令，然后将指令译码，辩明它取的是哪一条指令。最后，它完成必要的操作来执行指令（有人认为在指令周期中还要包括一个附加的步骤来存储结果，这里我们把该操作当作执行功能的一部分）。每一个功能读取、译码和执行都包括一个或多个操作。,2.3 I

23、nstruction Cycle,Lets start where the computer starts,with the microprocessor fetching the instruction from memory.First,the microprocessor places the address of the instruction on to the address bus.The memory subsystem inputs this address and decodes it to access the sired memory location.(We look

24、 at how this decoding occurs when we examine the memory subsystem in more detail later in this chapter.)我们从微处理器从存储器中取指令开始讲述。首先，微处理器把指令的地址放到地址总线上，然后，存储器子系统从总线上输入该地址并予以译码，去访问指定的存储单元。（译码是如何进行的，我们将在后面的章节中介绍存储器子系统是更为详细的讨论。）,2.3 Instruction Cycle,After the microprocessor allows sufficient time for memory

25、to decode the address and access the requested memory location,the microprocessor asserts a READ control signal.The READ signal is a signal on the control bus which the microprocessor asserts when it is ready to read data from memory or an I/O device.(Some processors have a different name for this s

26、ignal,but all microprocessors have a signal to perform this function.)Depending on the microprocessor,the READ signal may be active high(asserted-1)or active low(asserted-0).当微处理器为存储器留出充足的时间来对地址译码和访问所需的存储单元之后，微处理器发出一个读（READ）控制信号。当微处理器准备好可以从存储器或是I/O设备读数据时，它就在控制总线上发一个读信号。（一些处理器对于这个信号有不同的名字，但所有处理器都有这样的

27、信号来执行这个功能。）根据微处理器的不同，读信号可能是高电平有效（信号=1），也可能是低电平有效（信号=0）。,2.3 Instruction Cycle,When the READ signal is asserted,the memory subsystem places the instruction code to be fetched onto the computer systems data bus,The microprocessor then inputs this data from the bus and stores it in one of its internal

28、registers.At this point,the microprocessor has fetched the instruction.读信号发出后，存储器子系统就把要取的指令码放到计算机的数据总线上，微处理器就从数据总线上输入该数据并且将它存储在其内部的某个寄存器中。至此，微处理器已经取得了指令。,2.3 Instruction Cycle,Next,the microprocessor decodes the instruction.Each instruction may require a different sequence of operations to execute t

29、he instruction.When the microprocessor decodes the instruction,it determines which instruction it is in order to select the correct sequence of operations to perform.This is done entirely within the microprocessor;it does not use the system buses.接下来，微处理器对这条指令译码。每一条指令可能要有不同的操作序列来执行。当微处理器对该指令译码是，它确定处

30、理的是哪一条指令以便选择正确的操作序列去执行。这一步完全在微处理器内完成，不需要使用系统总线。,2.3 Instruction Cycle,Finally,the microprocessor executes the instruction.The sequence of operations to execute the instruction varies from instruction to instruction.The execute routine may read data from memory,write data to memory,read data from or

31、write data to an I/O device,perform only operations within the CPU,or perform some combination of these operations.We now look at how the computer performs these operations from a system perspective.最后，微处理器执行该指令。指令不同，执行的操作序列也不同。执行过程可以是从存储器读取数据，写数据到存储器，读或写数据到I/O设备，执行CPU内部操作或者执行多个上述操作的组合。下面我们从系统的角度来看计

32、算机是怎样执行这些操作的。,2.3 Instruction Cycle,To read data from memory,the microprocessor performs the same sequence of operations it uses to fetch an instruction from memory.After all,fetching an instruction is simply reading it from memory.Figure 2-2(a)shows the timing of the operations to read data from me

33、mory.微处理器从存储器读取数据所执行的操作序列，同从存储器中去一条指令是一样的。毕竟取指令就是简单地从存储器中读取它。图2-2(a)显示了从存储器中读取数据的操作时序。,2.3 Instruction Cycle,In Figure 2-2,notice the top symbol,CLK.This is the computer system clock;the microprocessor uses the system clock to synchronize its operations.The microprocessor places the address onto the

34、 bus at the beginning of a clock cycle,a 0/1 sequence of the system clock.One clock cycle later,to allow time for memory to decode the address and access its data,the microprocessor asserts the READ Signal.在图2-2中，注意最上面的符号CLK，它是计算机的系统时钟，微处理器用系统时钟使其操作同步。在一个时钟周期（系统时钟的0/1序列）的开始位置，微处理器将地址放到总线上。一个时钟周期（允许存

35、储器对地址译码和访问数据的时间）之后，微处理器才发出读信号。,2.3 Instruction Cycle,2.3 Instruction Cycle,This causes memory to place its data onto the system data bus.During this clock cycle,the microprocessor reads the data off the system bus and stores it in one of its registers.At the end of the clock cycle it removes the add

36、ress from the address bus and deasserts the READ signal.Memory then removes the data from the data bus,completing the memory read operation.这使得存储器将数据放到数据总线上。在这个时钟周期之内，微处理器从系统总线上读取数据，并存储到它的某个寄存器中。在这个时钟周期结束时，微处理器撤消地址总线上的地址，并撤消读信号。然后存储器从数据总线上撤消数据，也就完成了存储器的读操作。,The timing of the memory write operation i

37、s shown in Figure 2-2(b).The processor places the address and data onto the system buses during the first clock cycle.The microprocessor then asserts a WRITE control signal(or its equivalent)at the start of the second clock cycle.Just as the READ signal causes memory to read data,the WRITE signal tr

38、iggers memory to store data.存储器写操作的时序如图2-2(b)所示。在第一个时钟周期，处理器将地址和数据放到总线上，然后在第二个时钟周期开始 时发出一个写（WRITE）控制信号（或与之等价的信号）。像读信号促使存储器读取数据一样，写信号促使存储器存储数据。,2.3 Instruction Cycle,2.3 Instruction Cycle,Some time during this cycle,memory writes the data on the data bus to the memory location whose address is on the

39、 address bus.At the end of this cycle,the processor completes the memory write operation by removing the address and data from the system buses and deasserting the WRITE signal.在这个时钟周期的某个时刻，存储器将数据总线上的数据写入地址总线指示的存储单元内。当这个时钟周期结束，微处理器从系统总线上撤消地址、数据及写信号后，就完成了存储器的写操作。,The I/O read and write operations are

40、 similar to the memory read and write operations.A processor may use either memory mapped I/O or isolated I/O.If the processor supports memory mapped I/O,it follows the same sequences of operations to input or output data as to read data from or write data to memory,the sequences shown in Figure 2-2

41、.(Remember,in memory mapped I/O,the processor treats an I/O port as a memory location,so it is reasonable to treat an I/O data access the same as a memory access.)使用单独I/O的处理器遵循同样的处理过程，但是另有一个控制信号用以区别是I/O访问还是存储器访问（使用单独I/O的CPU允许一个存储单元和某个I/O端口具有相同的地址，因此需要这一额外的信号加以区分）。,2.3 Instruction Cycle,2.3 Instructi

42、on Cycle,Processors that use isolated I/O follow the same process but have a second control signal to distinguish between I/O and memory accesses.(CPUs that use isolated I/O can have a memory location and an I/O port with the same address,which makes this extra signal necessary.)使用单独I/O的处理器遵循同样的处理过程

43、，但是另有一个控制信号用以区别是I/O访问还是存储器访问（使用单独I/O的CPU允许一个存储单元和某个I/O端口具有相同的地址，因此需要这一额外的信号加以区分）。,Finally,consider instructions that are executed entirely within the microprocessor.The INAC instruction of the Relatively Simple CPU,and the MOV r1,r2 instruction of the 8085 microprocessor,can be executed without acce

44、ssing memory or I/O devices.As with instruction decoding,the execution of these instructions does not make use of the system buses.最后，考虑一下完全在微处理器内部执行的指令。相对简单CPU的INAC指令和8085的MOV r1，r2指令的执行都不要访问存储器和I/O设备。按照指令译码的结果，这些指令的执行不会用到系统总线。,2.3 Instruction Cycle,New Words&Expressions:latch v.闭锁,锁存program counte

45、r 程序计数器instruction register 指令寄存器operand n.操作数increment n.增量,加1flag register 标志寄存器pipeline n.流水线microsequenced 微层序的local bus 局部总线,Abbreviations:ALU(Arithmetic Logic Unit)算术逻辑单元,2.4 CPU Organization,The CPU controls the computer.It fetches instructions from memory,supplying the address and control si

46、gnals needed by memory to access its data.The CPU decodes the instruction and controls the execution procedure.It performs some operations internally,and supplies the address,data,and control signals needed by memory and I/O devices to execute the instruction.Nothing happens in the computer unless t

47、he CPU causes it to happen.CPU控制整个计算机。它从存储器中取指令，提供存储器需要的地址和控制信号。CPU对指令译码并且控制整个执行过程。它执行一些内部操作，并且为存储器和I/O设备执行指令提供必要的地址、数据和控制信号。除非CPU激发，否则，计算机什么事情都不会发生。,2.4 CPU Organization,Internally,the CPU has three sections,as shown in Figure 2-3.The register sections,as its name implies,includes a set of register

48、s and a bus or other communication mechanism.The registers in a processors instruction set architecture are found in this section of the CPU.The system address and data buses interact with this section of the CPU.The register section also contains other registers that are not directly accessible by

49、the programmer.The relatively simple CPU includes registers to latch the address being accessed in memory and a temporary storage register,as well as other registers that are not a part of its instruction set architecture.,CPU内部有三大分区，如图2-3所示。寄存器区,顾名思义，它包括一组寄存器、一条总线或其他通信机制。微处理器指令集结构中的寄存器就属于CPU的这一分区。系

50、统的地址和数据总线与寄存器交互。此分区还包括程序员不能直接访问的一些寄存器。相对简单CPU含有寄存器用以锁存正在访问的存储器地址，还有暂存器以及指令集结构中没有的其他寄存器等。,2.4 CPU Organization,During the fetch portion of the instruction cycle,the processor first outputs the address of the instruction onto the address bus.The processor has a register called the program counter;the