有限状态机的设计.ppt

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1、第8章 有限状态机的设计,Verilog HDL数字系统设计及仿真,2,本章内容,有限状态机的类型一段式、两段式和三段式状态机写法状态编码,3,有限状态机的类型,moore型，也称为摩尔型mealy型，也称为米利型,4,moore型红绿灯,状态转换图,5,模型代码,module trafficlight1(clock,reset,red,yellow,green);input clock,reset;/输入时钟和复位信号output red,yellow,green;/输出红黄绿的驱动信号reg red,yellow,green;reg 1:0 current_state,next_state

2、;/保存当前状态和下一状态parameter red_state=2b00,yellow_state=2b01,green_state=2b10,delay_r2y=4d8,delay_y2g=4d3,delay_g2r=4d11;/参数声明,6,/第一段always，用于把下一状态赋值给当前状态always(posedge clock or posedge reset)begin if(reset)current_state=red_state;else current_state=next_state;end,7,/第二段always，用于根据当前状态判断下一状态，并产生输出always(

3、current_state)begin case(current_state)red_state:begin red=1;yellow=0;green=0;repeat(delay_r2y)(posedge clock);next_state=yellow_state;end,8,完成状态描述,yellow_state:begin red=0;yellow=1;green=0;repeat(delay_y2g)(posedge clock);next_state=green_state;end green_state:begin red=0;yellow=0;green=1;repeat(de

4、lay_g2r)(posedge clock);next_state=red_state;end default:begin red=1;yellow=0;green=0;next_state=red_state;end endcaseendendmodule,9,测试信号,initial clock=0;always#10 clock=clock;initialbegin reset=1;#1 reset=0;/产生一个复位信号沿#10000 reset=1;/主要工作时间#20$stop;end,10,功能仿真时序仿真,11,增加一个可变计数器,always(posedge clock o

5、r posedge reset)begin if(reset)light_count=0;else if(light_count=light_delay)/达到规定的计数值light_delay时置1 light_count=1;else light_count=light_count+1;end,12,case(current_state)red_state:begin red=1;yellow=0;green=0;light_delay=red_delay;if(light_count=light_delay)next_state=yellow_state;end yellow_state

6、:begin red=0;yellow=1;green=0;light_delay=yellow_delay;if(light_count=light_delay)next_state=green_state;end,13,green_state:begin red=0;yellow=0;green=1;light_delay=green_delay;/延迟时间被赋值为green时的延迟 if(light_count=light_delay)/达到延迟时间变为下一状态 next_state=red_state;end,14,mealy型红绿灯,状态转换图,15,设计模块,module traf

7、ficlight3(clock,reset,x,red,yellow,green);input clock,reset;input x;/多添加了一个输入端xoutput red,yellow,green;reg red,yellow,green;reg 1:0 current_state,next_state;parameter red_state=2b00,yellow_state=2b01,green_state=2b10,delay_r2y=4d8,delay_y2g=4d3,delay_g2r=4d11;,16,always(posedge clock or posedge rese

8、t)/原态和新态的转换begin if(reset)current_state=red_state;else current_state=next_state;end,17,always(current_state or x)begin case(current_state)red_state:begin red=1;yellow=0;green=0;if(x=1)/红灯时若x为1，则把下一状态指向黄灯 begin repeat(delay_r2y)(posedge clock);next_state=yellow_state;end end,18,yellow_state:begin red

9、=0;yellow=1;green=0;repeat(delay_y2g)(posedge clock);next_state=green_state;end green_state:begin red=0;yellow=0;green=1;repeat(delay_g2r)(posedge clock);next_state=red_state;end,19,default:begin red=1;yellow=0;green=0;next_state=red_state;end endcaseendendmodule,20,仿真波形,21,一段式状态机,检测输入信号0110 状态转换图,2

10、2,状态转换表,23,声明部分,module fsm_seq1(x,z,clk,reset);input x,clk,reset;output z;reg z;reg2:0state;parameter s0=d0,s1=d1,s2=d2,s3=d3,s4=d4;,24,一段always,always(posedge clk or posedge reset)/仅有一段always begin if(reset)/复位信号有效 begin state=s0;/回到初始状态 z=0;/z输出0 end,25,S0状态,S1状态,else casex(state)s0:begin if(x=1)b

11、egin state=s0;z=0;end else begin state=s1;z=0;end end,s1:begin if(x=0)begin state=s1;z=0;end else begin state=s2;z=0;end end,26,S2状态,S3状态,s2:begin if(x=0)begin state=s1;z=0;end else begin state=s3;z=0;end end,s3:begin if(x=0)begin state=s4;z=1;end else begin state=s0;z=0;end end,27,S4状态,结束,s4:begin

12、if(x=0)begin state=s1;z=0;end else begin state=s2;z=0;end end,default:state=s0;endcase endendmodule,28,功能仿真波形时序仿真波形,29,一段式特点,仅有一段always结构，里面包含了状态转换、复位和输出；always结构的敏感列表是时钟沿，所以最后的输出结构是以寄存器形式输出，即时序逻辑输出的,30,两段式状态机,声明部分,module fsm_seq2(x,z,clk,reset);input x,clk,reset;output z;reg z;reg2:0state,nstate;/s

13、tate表示原态，nstate表示新态parameter s0=d0,s1=d1,s2=d2,s3=d3,s4=d4;,31,第一段always,第二段always,always(posedge clk or posedge reset)begin if(reset)state=s0;else state=nstate;end,always(state or x)begin casex(state)s0:begin if(x=1)begin nstate=s0;z=0;end else begin nstate=s1;z=0;end end,32,s1,s2,s1:begin if(x=0)b

14、egin nstate=s1;z=0;end else begin nstate=s2;z=0;end end,s2:begin if(x=0)begin nstate=s1;z=0;end else begin nstate=s3;z=0;end end,33,s3,s4,s3:begin if(x=0)begin nstate=s4;z=1;end else begin nstate=s0;z=0;end end,s4:begin if(x=0)begin nstate=s1;z=0;end else begin nstate=s2;z=0;end end default:nstate=s

15、0;endcaseend,34,仿真波形,fsm_seq1的输出z发生在每个clk上升沿的位置，fsm_seq2的输出z发生在x变化的位置fsm_seq1的输出维持一个周期，fsm_seq2的输出维持半个周期。最后的输出采用组合逻辑电路,35,三段式状态机,除always外无区别,/第一段always，完成原态到新态的转换always(posedge clk or posedge reset)begin if(reset)state=s0;else state=nstate;end,36,/第二段always，指定新态的变化always(state or x)begin casex(state

16、)s0:begin if(x=1)nstate=s0;else nstate=s1;end s1:begin if(x=0)nstate=s1;else nstate=s2;end,s2:begin if(x=0)nstate=s1;else nstate=s3;end s3:begin if(x=0)nstate=s4;else nstate=s0;end s4:begin if(x=0)nstate=s1;else nstate=s2;end default:nstate=s0;endcaseend,37,always(state or x)/第三段always，指定不同状态下的输出beg

17、in casex(state)s0:z=0;s1:z=0;s2:z=0;s3:begin if(x=0)z=1;else z=0;end s4:z=0;default:z=0;endcaseend,38,Mealy型的五种输出敏感列表,always(state or x)if(state=xxx and x=yyy)always(state)always(nstate)always(posedge clk)case(state)always(posedge clk)case(nstate),39,时序图,40,Moore型的四种输出敏感列表,always(state)always(nstate

18、)always(posedge clk)case(state)always(posedge clk)case(nstate),41,时序图,42,状态编码的选择,二进制码 parameter s0=3b000,s1=3b001,s2=3b010,s3=3b011,s4=3b100;格雷码 parameter s0=3b000,s1=3b001,s2=3b011,s3=3b010,s4=3b110;独热码 parameter s0=5b00001,s1=5b00010,s2=5b00100,s3=5b01000,s4=5b10000;,43,独热码状态机,状态转换图,44,设计代码,声明部分,m

19、odule ex8_1(clock,reset,x,y1,y2);input clock,reset;input x;output y1,y2;reg y1,y2;reg3:0 cstate,nstate;/本例中采用独热码，当然使用二进制码也可parameter s0=4b0001,s1=4b0010,s2=4b0100,s3=4b1000;,45,/第一段always，原态变新态always(posedge clock or posedge reset)begin if(reset)cstate=s0;else cstate=nstate;end,46,/第二段always，状态转换alw

20、ays(cstate or x)begin case(cstate)s0:begin if(x=0)nstate=s1;else nstate=s3;end s1:begin if(x=0)nstate=s2;else nstate=s0;end,s2:begin if(x=0)nstate=s3;else nstate=s1;end s3:begin if(x=0)nstate=s0;else nstate=s2;end default:nstate=s0;endcaseend,47,s2:begin if(x=0)y1=0;else y1=0;end s3:begin if(x=0)y1=

21、0;else y1=1;end default:y1=0;endcaseend,/第三段always，产生输出always(cstate or x)begin case(cstate)s0:begin if(x=0)y1=1;else y1=0;end s1:begin if(x=0)y1=0;else y1=0;end,懒！,48,简化输出,always(cstate or x)/在输出比较简单时，也可以使用if来确定输出值begin if(cstate=s0 end,49,进一步精简,always(cstate or x)begin if(cstate=s0 end,50,功能仿真波形时序

22、仿真波形,51,格雷码状态机,状态转换图,52,声明部分,module ex8_2(clock,reset,a,z1,z2,z3,z4);input clock,reset;input a;output z1,z2,z3,z4;reg z1,z2,z3,z4;reg 1:0 cs,ns;parameter s0=2b00,s1=2b01,s2=2b11,s3=2b10;/格雷码,53,always(posedge clock or posedge reset)begin if(reset)cs=s0;else cs=ns;end,54,always(cs or a)begin case(cs)

23、s0:begin if(a=0)ns=s0;else ns=s1;end s1:begin if(a=0)ns=s0;else ns=s2;end,s2:begin if(a=0)ns=s0;else ns=s3;end s3:begin if(a=0)ns=s0;else ns=s3;end default:ns=s0;endcaseend,55,/第二个输出，使用时钟沿 和下一状态做敏感列表always(posedge clock)begin if(ns=s3 end,/第一个输出，使用时钟沿和当前状态做敏感列表always(posedge clock)begin if(cs=s3 end,56,/第三个输出，使用当前状态做敏感列表always(cs)begin if(cs=s3 end,/第四个输出，使用下一状态做敏感列表always(ns)begin if(ns=s3 end,57,仿真波形图,