数字电路英文版 第七单元.ppt

《数字电路英文版 第七单元.ppt》由会员分享，可在线阅读，更多相关《数字电路英文版 第七单元.ppt（73页珍藏版）》请在三一办公上搜索。

1、CHAPTER 7INTRODUCTION TO PROGRAMMABLE LOGIC DEVICE,ABEL(件描述语言的一种)Architecture(结构体)Array(阵列)Buffer(缓冲器)Cell(单元)Compiler(编辑器)Documentation file(使用说明文件)Fuse(熔丝)E2CMOS(电可擦除的CMOS)GAL(通用阵列逻辑器件)Input file(输入文件)Input/Output(I/O)(输入/输出),JEDEC file(标准数据格式文件)OLMC(输出逻辑宏单元)PAL(可编程阵列逻辑)PLA(可编程逻辑阵列)PLD(可编程逻辑器件)Pro

2、grammer(编程器)PROM(可编程只读存储器)Software(软件)Synthesis(综合)Tristate output buffer(三态输出缓冲器)ZIF socked(不用力插座),KEY TERMS,ABEL Advanced Bollean Expression Language.A software compiler language for PLD programming;a type of hardware description language(HDL).Architecture The internal functional arrangement of th

3、e elements that give a device its particular operating characteristics.,Array In a PLD,a matrix formed by rows of product-term lines and columns of input lines with a programmable cell at each junction.Buffer A circuit that prevents loading of an input or output.Cell A fused cross point of a row and

4、 columnn in a PLD.,Complier Software that translates from high-level language that uses words or symbols,such as HDL,into low-level machine language(1s and 0s).Documentation file The information from a computer that documents the final design after the input file has been processed.,E2CMOS Electrica

5、lly earsable CMOS(EECMOS).The circuit technology used for the reprogrammable cells in GAL.Fuse The programmable element in certain types of PLDs;also called a fusible link.GAL Generic array logic.A PLD with a reprogrammable AND array,a fixed OR array,and programmable output logic macrocells.,Input f

6、ile The information entered in a computer that describes logic design using a PLD programming language such as HDL.Input/Output(I/O)A terminal of a device that can be used as either an input or as an output.,OLMC Output logic marcocell.The programmable output logic in a GAL.PAL Programmable array lo

7、gic.A PLD with a programmable AND array and a fixed OR array.PLA Programmable logic array.A PLD with a programmable AND and OR array.,PLD Programmable logic device.Programmer An instrument that programs PLD using a JEDEC file downloaded from a computer running HDL software.Software Computer programs

8、;programs that instruct a computer what to do in order to carry out a given set of tasks.,Synthesis The software process of converting a circuit description to a standard JEDEC file for PLD programming.Tristate output buffer A logic circuit having three output states:HIGH,LOW,and high impedance(open

9、).,ZIF socket Zero insertion force socket.A type of socket used in most programmers that accepts a PLD package.,7.1 PLD ARRAYS AND CLASSIFICATIONS,Programmable logic devices(PLDs)are used in many applications to replace SSI and MSI circuits;they save space and reduce the actual number and cost of de

10、vices in a given design.,2,A PLD consist of a large array of AND gates and OR gates that can be programmed to achieve specified logic functions.Four types of devices that are classified as PLDs are the programmable read-only memory(PROM),the programmable logic array(PLA),the programmable array logic

11、(PAL),and the generic array logic(GAL).,3,Programmable Arrays,The OR Array,A,A,B,B,X1,X2,X3,Fusible link,4,A,A,B,B,X1=A+B,X2=A+B,X3=A+B,5,The AND Array,A,A,B,B,X1,X2,X3,6,A,A,B,B,X1=AB,X2=AB,X3=AB,7,Classification of PLDs,Programmable Read-Only Memory,FixedAND array,ProgrammableOR array,Output 1,Inp

12、ut 1,Input 2,Input n,Output 2,Output m,8,Programmable Logic Array(PLA),ProgrammableAND array,ProgrammableOR array,Output 1,Input 1,Input 2,Input n,Output 2,Output m,9,Programmable Array Logic(PAL),ProgrammableAND array,Fixed OR array andoutput logic,Output 1,Input 1,Input 2,Input n,Output 2,Output m

13、,10,Generic Logic Array(GAL),ProgrammableAND array,Fixed OR array andProgrammableoutput logic,Output 1,Input 1,Input 2,Input n,Output 2,Output m,11,7.2 PROGRAMMABLE ARRAY LOGIC(PAL),The PAL and the GAL are the most common PLDs used for logic implementation.As you learned in the last section,the PAL

14、in its basic form is a PLD with a one-time programmable AND array and fixed OR array.In this section,you will learn how PALs are used to produce specified combinational logic functions and examine a specific PAL.,12,PAL Operation(SOP),A,A,B,B,X,13,Implementing a Sum-of-Products Expression X=AB+AB+AB

15、,A,A,B,B,X,14,Simplified Symbols,A,A,B,B,X,A,B,4,AB,AB,AB,15,X,X,X,X,X,X,Programmable Array Logic(PAL),ProgrammableAND array,Fixed OR array,Output 1,Input 1,Input 2,Input n,Output 2,Input 3,Output m,Outputlogic,Outputlogic,Outputlogic,16,PAL Output Combination Logic,Output,From ANDGate array,Tristat

16、e control,(a)Combination output(active-LOW).,17,I/O,From ANDGate array,Tristate control,(b)Combination input/output(active-LOW).,18,I/O,From ANDGate array,Tristate control,(c)Programmable polarity output,Programmable fuse,19,Standard PAL Numbering,PAL 10L8,Programmable array logic,Ten inputs,Eight o

17、utputs,Active-LOW output,20,7.3 GENERIC ARRAY LOGIC(GAL),The GAL in its basic form is a PLD with a reprogrammable AND array,a fixed OR array,and programmable output logic.In this section,basic concepts are introduced and Section 7-4 and 7-5 specific GALs are examined.GAL Operation electrically erasa

18、ble CMOS(E2CMOS),21,A,A,B,B,X,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,22,A,A,B,B,Off,On,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,On,On,On,On,On,A

19、B,AB,AB,X=AB+AB+AB,23,The GAL Block Diagram,E2CMOSProgrammableAND array,I/O 1,Input 1,Input 2,Input n,I/O 2,Input 3,I/O m,OLMC,OLMC,OLMC,24,Standard GAL Numbering,GAL 16V8,Generic array logic,Sixteen inputs,Eight outputs,Variable-output configuration,25,7.4 THE GAL22V10,The various GALs all have the

20、 same type of programmable array.The differ in the size of the array,in the type of OLMCs,and in operating parameters such as speed and power dissipation.In this section,a popular generic array logic device,the GAL22V10,is discussed.,26,Logic Diagram,1-of-4multiplexer,1-of-2multiplexer,Flip-Flop,OLM

21、C,S1,S0,S1,I/O,27,The Output Logic Macrocells(OLMCs)As stated in the discussion of GALs,an OLMC contains programmable logic circuits that can be either for a combinational output or input or for a registered output.,28,1-of-4multiplexer,1-of-2multiplexer,Flip-Flop,OLMC,S1,S0,S1,I/O,(a)Active-LOW out

22、put S1=1,S0=0,29,1-of-4multiplexer,1-of-2multiplexer,Flip-Flop,OLMC,S1,S0,S1,I/O,(b)Active-HIGH output S1=1,S0=1,30,Input,Output,Tristate,control,HIGH,LOW,HIGH,Active state,LOW,(a),HIGH,LOW,HIGH,Active state,High-impedance state,(b),31,Output or Input Selection,1-of-4multiplexer,1-of-2multiplexer,Fl

23、ip-Flop,OLMC,S1,S0,S1,HIGH,Output,(a)Output,32,1-of-4multiplexer,1-of-2multiplexer,Flip-Flop,OLMC,S1,S0,S1,LOW,Input,(b)Input,33,1-of-4multiplexer,1-of-2multiplexer,Flip-Flop,OLMC,S1=1,S0=1,S1=1,HIGH,X=ABCD+ABCD+ABCD+ABCD+ABCD+,X,ABCD,ABCD,ABCD,ABCD,ABCD,ABCD,ABCD,Active HIGH,Related Problem Write t

24、he SOP expression for the output if S0=0,S1=1,(Active LOW),1-of-4multiplexer,1-of-2multiplexer,Flip-Flop,OLMC,S1=1,S0=0,S1=1,HIGH,X=ABCD+ABCD+ABCD+ABCD+ABCD+ABCD,X,ABCD,ABCD,ABCD,ABCD,ABCD,ABCD,(Active LOW),Example 7-6 Show how the following 6-variable SOP function is implemented with the AL22V10X=A

25、BCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF,0 3,4 7,B,B,C,C,D,D,E,E,F,F,8 11,12 15,16 19,20 23,40 43,A,1,O,HIGH,S0=1,S1=1,OLMC,7.6 PLD PROGRAMMING,As you have learned,PLAs are programmed by leaving specified fusible links intact and blowing open all others.GALs are programmed in a similar way ex

26、cept the E2CMOS cells are turned on or off.The logic functions to be implemented determines which cells are affected.,34,In order to program a PLA or GAL,the following items are required:a computer,programming software,and a PLD programmer.,Computer:Any computer that meets the software and programme

27、r specifications can be used.,35,Software:The software packages for PLD programming are called logic compliers.,The Programmer:The programmer has a software driver program that reads JEDEC file generated by the logic complier and converts it to instructions for applying required voltages to specifie

28、d PLD pins to alter the specified cells in the array as directed by the fuse map.,36,START,Design the,logic circuit,Enter design,into computer,Syntax or,Other errors?,Complier,file and,Design,simulation,Design,flaw?,processes input,minimizes logic,Debug,Edit,Yes,No,No,Yes,37,Complier creates,JEDEC f

29、ile(fuse map),Download to,programmer,Programmer“burns”,fuse map into PLD,array,Complier generates,documentation file,38,The Programming Process,Entering the Design:The logic design is entered into the computer by creating an input or source file.,Running the Software:The software complier processes

30、and translates the input file and minimizes the logic.,39,Programming the Device:When the design is finalized,the compiler creates a fuse map(JEDEC file)and downloads it to the programmer.,40,7.7 PLD SOFTWARE,As mentioned earlier,there are several software packages for implementing logic designs in

31、PLDs.ABEL is commonly used hardware description languages(HDLs).,41,Introduction to ABEL:ABEL,which is the acronym for Advanced Boolean Expression Language,allows logic designs to be implemented in programmable in programmable logic devices.,42,Logic Design Entry:ABEL provides three different format

32、s for describing and entering a logic design from the from the computer keyboard:equations,truth tables,and state diagrams.,43,Design Simulation:Once a logic circuit design has been entered,its operation can be simulated using test vectors to make sure there are no design errors.,44,Logic Synthesis:

33、The software process of converting a circuit description in the form of equations,truth tables,or state diagrams to a standard JEDEC file format required to actually implement the design in a PLD is called logic synthesis.,45,Boolean Operations:,Logic Operation ABEL Symbol,NOT!,AND&,OR#,XOR$,46,Stan

34、dard Boolean ABEL,A!A,AB A&B,A+B A#B,+,A B A$B,47,EXAMPLE 7-7 Write each of the following logic expressions in ABEL:X=ABC+ABC+AB+BCY=(A+B+C+D)(A+B+C)Solution X=A&!B&C#!A!B!C#A&B#!B&CY=(!A#B#!C#D)&(A#B#C)RP:W=X+Y,Where X=ABC,Y=A+B+C,48,EXAMPLE 7-8,Multiplexer,A3,A2,A1,A0,B3,B2,B1,B0,Y3,Y2,Y1,Y0,C3,C2

35、,C1,C0,S1,S0,49,Select Input Data Output S1 S0 Y3 Y2 Y1 Y0,0 1 A3 A2 A1 A0,1 0 B3 B2 B1 B0,1 1 C3 C2 C1 C0,50,Solution:Y3=A3S1S0+B3S1S0+C3S1S0 Y2=A2S1S0+B2S1S0+C2S1S0 Y1=A1S1S0+B1S1S0+C1S1S0 Y0=A0S1S0+B0S1S0+C0S1S0,Y3=A3&!S1&S0#B3S1&!S0#C3&S1&S0,Y2=A2&!S1&S0#B2S1&!S0#C2&S1&S0,Y1=A1&!S1&S0#B1S1&!S0#C

36、1&S1&S0,Y0=A0&!S1&S0#B0S1&!S0#C0&S1&S0,The equations in ABEL format are,51.,Sets with the following declaration:,A=A3,A2,A1,A0;,B=B3,B2,B1,B0;,C=C3,C2,C1,C0;,Y=Y3,Y2,Y1,Y0;,S=S1,S0;,Y=(S=1),52,Truth Tables,TRUTH_TABLE(A,B,C,D X1,X2),TRUTH_TABLE(A,B X),1,0 1;,0,1 1;,0,0 0;,1,1 0;,The XOR gate,53,EXAM

37、PLE 7-9 BCD-to-7-segment decoder,BCD-to-7-segmentdecoder,D,C,B,A,a,b,c,d,e,f,g,7-segment display,a,b,c,d,e,f,g,54,TRUTH_TABLE(D,C,B,A,-a,b,c,d,e,f,g),0,0,0,0,-1,1,1,1,1,1,0;,0,0,0,1,-0,1,1,0,0,0,0;,0,0,1,0,-1,1,0,1,1,0,1;,0,0,1,1,-1,1,1,1,0,0,1;,0,1,0,0,-0,1,1,0,0,1,1;,0,1,0,1,-1,0,1,1,0,1,1;,0,1,1,

38、0,-1,0,1,1,1,1,1;,0,1,1,1,-1,1,1,0,0,0,0;,1,0,0,0,-1,1,1,1,1,1,1;,1,0,0,1,-1,1,1,1,0,1,1;,55,TRUTH_TABLE(BCD-a,b,c,d,e,f,g),0-1,1,1,1,1,1,0;,1-0,1,1,0,0,0,0;,2-1,1,0,1,1,0,1;,3-1,1,1,1,0,0,1;,4-0,1,1,0,0,1,1;,5-1,0,1,1,0,1,1;,6-1,0,1,1,1,1,1;,7-1,1,1,0,0,0,0;,8-1,1,1,1,1,1,1;,9-1,1,1,1,0,1,1;,BCD=D,C,B,A;,56,Figure 7-18,Thomas L.FloydDigital Fundamentals,8e,Copyright 2003 by Pearson Education,Inc.Upper Saddle River,New Jersey 07458All rights reserved.,s1,s1,s0,s0,A1,A0,B0,