网络计算与高效算法.ppt

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1、AN Efficient Implementation of the InfiniBand Link Layer,一种高效的InfiniBand链路层实现,Company Logo,Contents,简介,1,传统链路层与实现的对比,2,FIFO芯片的实现,3,小结,4,Company Logo,简介,This paper presents the design and implementation of the Link layer of an InfiniBand HCA.For the effcient implementation of the receiver logic,high-

2、speed packet buffering architecture with a novel FIFO circuit is proposed.The new architecture enables the eflicient utilization of the InfiniBand handwidth and the reduction of hardware cost as well as power consumption.,Company Logo,简介,Link layeris responsible for sending and receiving data across

3、 the fabric at the packet-level.handles flow control at the physical link-levelBufferingError detectionPacket routing within the local subnetAddress decode,Company Logo,简介,In this paper we deal with：Resource managementsFlow controlBuffer arbitrationhigh-speed packet processingThe new architecture re

4、sults in the reduction of the memory size and controller complexity.In addition,the packet processing time by the receiver side is significantly reduced.,Company Logo,Text i here,Text in ere,Text in here,Text in ere,传统链路层,all fields of a packet are stored in a temporary bufferthe packet is analyzed

5、and error-checked by the inspection logicIf there is any error,it is indicated by the signal from the inspection logic and the corresponding packet is discardedIf no error is detected,the packet is sent to the corresponding FIFO toward upper layer as the arrow ofthe packet is sent to the upper layer

6、 as the arrows of,Company Logo,传统链路层,Disadvantage：it may be inefficient or even impossible to apply the architecture to new standards that require very high bandwidth ranging from several Gbps to several tens of Gbps.This is because the Memory and Controller block in Fig.2 cannot afford to process a

7、ll incoming packets rapidly and becomes the bottleneck of the receiver resulting in the increase of the processing latency.,Company Logo,Text i here,Text in ere,Text in here,Text in ere,新型链路层,The Memory and Controller block,bottleneck in the conventional approach,is removed in the proposed architect

8、ure.When the input packet is being stored,the inspection logic performs real-time checks about various fields of the packet and accumulates the CRC value calculated at every clock cycle.If there is an error at the end or in the middle of packet receiving,the packet data being stored into the FIFO is

9、 immediately discarded.The upper layer also detects errors while pulling out data from the FIFO.If an error is detected,the whole packet is discarded from the FIFO.,Company Logo,Text i here,Text in ere,Text in here,Text in ere,FIFO芯片的实现,write-data-inread-data-outwrite-enable-inread-enable-infull-out

10、empty-outwaddrwaddr_boundwaddr_loadwaddr_bound_loadraddr_plus_1raddr_plus_1_regwaddr_plus_1waddr_bound_plus_1upper_layer_discard,Company Logo,Text i here,Text in ere,Text in here,Text in ere,小结,This paper presents an implementation of the InfiniBand Link layer and proposes a high-speed packet buffer

11、ing architecture with a new FIFO circuit.The proposed architecture and FIFO remove temporary buffers and consequently reduce hardware cost and power consumption.In addition,the Link layer core can efficiently utilize the available bandwidth of InfiniBand.The proposed architecture and FIFO are also applicable to the state-of-the-art I/0 standards that have high-speed switched fabric architectures such as HyperTransport,RapidIO,PCI Express,Fibre Channel,Gigabit Ethernet,etc.,Thank You!,