993计算机组成与结构.ppt

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1、,计算机组成与结构,Lecture 20 层次结构的存储器Reading:7.1-7.3Homework:7.1-7.4,7.9,7.12,7.14,7.39,本课件内容源于美国Lafayette 大学John Nestor教授的课件,ECE 313 Fall 2006,Lecture 20-Memory,2/89,Roadmap for the term:major topics,Overview/Abstractions and TechnologyInstruction setsLogic&arithmeticPerformanceProcessor ImplementationSing

2、le-cycle implemenatationMulticycle implementationPipelined ImplementationMemory systems 3Input/Output,ECE 313 Fall 2006,Lecture 20-Memory,3/89,Outline-Memory Systems,Overview 3MotivationGeneral Structure and Terminology(术语)Memory TechnologyStatic RAMDynamic RAMDisksCache MemoryVirtual Memory,ECE 313

3、 Fall 2006,Lecture 20-Memory,4/89,Memory Systems-the Big Picture,Memory provides processor withInstructionsData Problem:memory is too slow and too small,ECE 313 Fall 2006,Lecture 20-Memory,5/89,Memory Hierarchy-the Big Picture,Problem:memory is too slow and too smallSolution:memory hierarchy（层次）-分层存

4、储器,Fastest,Slowest,Smallest,Biggest,Highest,Lowest,ECE 313 Fall 2006,Lecture 20-Memory,6/89,Why Hierarchy Works,The principle of locality（局部性原理）Programs access a relatively small portion of the address space at any instant of time.-在任一瞬间，程序只访问地址空间中的一小部分Temporal locality:recently accessed data is lik

5、ely to be used againSpatial locality:data near recently accessed data is likely to be used soonResult:the illusion(幻想)of large,fast memory,ECE 313 Fall 2006,Lecture 20-Memory,7/89,Memory Hierarchy-Speed vs.Size,ECE 313 Fall 2006,Lecture 20-Memory,8/89,Memory Hierarchy Terminology术语,Processor,Blocks

6、of Data,数据复制每次只在两个相邻层次间进行,ECE 313 Fall 2006,Lecture 20-Memory,9/89,存储器层次结构的几个术语,Hit:处理器需要的数据出现在高层的某个块中(green block)Hit Rate:the fraction of memory accesses that“hit”Hit Time:time to access the upper level(time to determine hit/miss+access time)Miss:data must be retrieved from block in lower level(or

7、ange block)缺失率 Miss Rate=1-(Hit Rate)Miss Penalty:Time to replace block in upper level+Time to deliver data to the processorHit Time Miss Rate,ECE 313 Fall 2006,Lecture 20-Memory,10/89,Typical Memory Hierarchy-Details,Registers-Small,fastest on-chip storageManaged by compiler and run-time systemCach

8、e-Small,fast on-chip storageAssociative lookup-managed by hardwareMemory-Slower,Larger off-chip storageLimited size 16Gb-managed by hardware,OSDisk-Slowest,Largest off-chip storageVirtual memory simulate a large memory using disk,hardware,and operating systemFile storage-store data files using opera

9、ting system,ECE 313 Fall 2006,Lecture 20-Memory,11/89,存储器系统影响计算机的许多方面,用于构造存储器系统的概念影响到计算机的许多方面，如：OS对存储器和I/O如何管理编译器如何生成代码应用程序如何使用计算机性能评估因而，设计人员花费了相当的精力开发复杂的机制以提高存储器系统的性能本章进行了大量抽象和简化,ECE 313 Fall 2006,Lecture 20-Memory,12/89,Outline-Memory Systems,OverviewMotivationGeneral Structure and TerminologyMemo

10、ry Technology 3Static RAMDynamic RAMCache MemoryVirtual Memory,ECE 313 Fall 2006,Lecture 20-Memory,13/89,Memory Types,Static RAMStorage using latch circuits(门锁电路）Values saved while power on Dynamic RAMStorage using capacitors（电容）Values must be refreshed,bit,bit,word/row select,1,0,0,1,word/row selec

11、t,bit,C,ECE 313 Fall 2006,Lecture 20-Memory,14/89,Tradeoffs-Static vs.Dynamic RAM,Static RAM(SRAM)-used for L1,L2 cacheFast-0.5-25ns access time(less for on-chip)Larger,More ExpensiveHigher power consumptionDynamic RAM(DRAM)-used for PC main memorySlower-80-250ns access time*Smaller,CheaperLower pow

12、er consumption,ECE 313 Fall 2006,Lecture 20-Memory,15/89,DRAM Organization,Row Decoder,Column Selector/Latch/IO,RowAddress,ColumnAddress,/RAS,/CAS,DATA,ECE 313 Fall 2006,Lecture 20-Memory,16/89,DRAM Read Operation,Row Decoder,Column Selector/Latch/IO,RowAddress,ColumnAddress,/RAS,/CAS,DATA,ECE 313 F

13、all 2006,Lecture 20-Memory,17/89,DRAM Trends（趋势）,RAM size:4X every 3 yearsRAM speed:2X every 10 years,DRAMYearSizeCycle Time198064 Kb250 ns1983256 Kb220 ns19861 Mb190 ns19894 Mb165 ns199216 Mb145 ns199564 Mb120 ns1997?128 Mb?ns1999?256 Mb?ns,1980-1995Size change:1000:1!,1980-1995Speed change:2:1!,EC

14、E 313 Fall 2006,Lecture 20-Memory,18/89,The Processor/Memory Speed Gap,DRAM9%/yr.(2X/10 yrs),1,10,100,1000,1980,1981,1983,1984,1985,1986,1987,1988,1989,1990,1991,1992,1993,1994,1995,1996,1997,1998,1999,2000,DRAM,CPU,1982,Processor-MemoryPerformance Gap:(grows 50%/year),Performance,Time,“Moores Law”,

15、ECE 313 Fall 2006,Lecture 20-Memory,19/89,定位导致速度差异的原因Addressing the Speed Gap,Latency depends on physical limitationsBandwidth can be increased using:并行Parallelism transfer(传输)more bits/wordBurst transfers-transfer successive words on each cycle在每个周期中传输连续的机器字So.use bandwidth to support memory hierar

16、chy(层次)!Use cache to support locality of referenceDesign hierarchy to transfer large blocks of memory,ECE 313 Fall 2006,Lecture 20-Memory,20/89,Current DRAM Parts,Synchronous同步的 DRAM(SDRAM)-clocked transfer of bursts of data starting at a specific addressDouble-Data Rate SDRAM-transfer two bits/cloc

17、k cycleQuad（方形）-Data Rate SDRAM-transfer four bits/clock cycleRambus RDRAM-High-speed interface for fast transfersCurrent PCs use some form of SDRAM/RDRAMSDRAM w/PC100 or PC133 memory busRDRAM w/PC800 memory bus,ECE 313 Fall 2006,Lecture 20-Memory,21/89,Memory Configuration in Current PCs,Processor,

18、SystemController,L1 Cache,Main Memory(DRAM),L2/L3 Cache(SRAM),(I/O Bus),ECE 313 Fall 2006,Lecture 20-Memory,22/89,主存是以存储芯片为基本单位构成,用 16K 1位 的存储芯片组成 64K 8位 的存储器,32片,ECE 313 Fall 2006,Lecture 20-Memory,23/89,存储芯片的译码驱动方式-线选法,ECE 313 Fall 2006,Lecture 20-Memory,24/89,存储芯片的译码驱动方式-重合法,0,0,ECE 313 Fall 2006

19、,Lecture 20-Memory,25/89,静态 RAM(SRAM)基本电路,A 触发器非端,A 触发器原端,T1 T4,ECE 313 Fall 2006,Lecture 20-Memory,26/89,静态 RAM 基本电路的 读 操作,ECE 313 Fall 2006,Lecture 20-Memory,27/89,静态 RAM 基本电路的 写 操作,ECE 313 Fall 2006,Lecture 20-Memory,28/89,静态 RAM 芯片举例-Intel 2114,存储容量1K4位,这些存储元件应该如何排列？才能给出一个存储单元的地址而一次读出4位信息。1、立体；2

20、、平面,ECE 313 Fall 2006,Lecture 20-Memory,29/89,Intel 2114 RAM 矩阵(64 64)读,ECE 313 Fall 2006,Lecture 20-Memory,30/89,Intel 2114 RAM 矩阵(64 64)读,ECE 313 Fall 2006,Lecture 20-Memory,31/89,Intel 2114 RAM 矩阵(64 64)读,ECE 313 Fall 2006,Lecture 20-Memory,32/89,Intel 2114 RAM 矩阵(64 64)读,ECE 313 Fall 2006,Lectur

21、e 20-Memory,33/89,Intel 2114 RAM 矩阵(64 64)读,ECE 313 Fall 2006,Lecture 20-Memory,34/89,Intel 2114 RAM 矩阵(64 64)读,ECE 313 Fall 2006,Lecture 20-Memory,35/89,Intel 2114 RAM 矩阵(64 64)读,ECE 313 Fall 2006,Lecture 20-Memory,36/89,Intel 2114 RAM 矩阵(64 64)读,ECE 313 Fall 2006,Lecture 20-Memory,37/89,Intel 2114

22、 RAM 矩阵(64 64)读,ECE 313 Fall 2006,Lecture 20-Memory,38/89,Intel 2114 RAM 矩阵(64 64)写,ECE 313 Fall 2006,Lecture 20-Memory,39/89,Intel 2114 RAM 矩阵(64 64)写,ECE 313 Fall 2006,Lecture 20-Memory,40/89,Intel 2114 RAM 矩阵(64 64)写,ECE 313 Fall 2006,Lecture 20-Memory,41/89,Intel 2114 RAM 矩阵(64 64)写,ECE 313 Fall

23、 2006,Lecture 20-Memory,42/89,Intel 2114 RAM 矩阵(64 64)写,ECE 313 Fall 2006,Lecture 20-Memory,43/89,Intel 2114 RAM 矩阵(64 64)写,ECE 313 Fall 2006,Lecture 20-Memory,44/89,Intel 2114 RAM 矩阵(64 64)写,ECE 313 Fall 2006,Lecture 20-Memory,45/89,Intel 2114 RAM 矩阵(64 64)写,ECE 313 Fall 2006,Lecture 20-Memory,46/8

24、9,Intel 2114 RAM 矩阵(64 64)写,ECE 313 Fall 2006,Lecture 20-Memory,47/89,动态 RAM(DRAM)-基本单元电路,读出与原存信息相反,读出时数据线有电流 为“1”,写入与输入信息相同,写入时CS充电 为“1”放电 为“0”,T,无电流,有电流,ECE 313 Fall 2006,Lecture 20-Memory,48/89,动态 RAM 芯片举例-三管动态 RAM 芯片(Intel 1103)读,读 写 控 制 电 路,ECE 313 Fall 2006,Lecture 20-Memory,49/89,三管动态 RAM 芯片(

25、Intel 1103)写,ECE 313 Fall 2006,Lecture 20-Memory,50/89,三管动态 RAM 芯片(Intel 1103)写,ECE 313 Fall 2006,Lecture 20-Memory,51/89,三管动态 RAM 芯片(Intel 1103)写,ECE 313 Fall 2006,Lecture 20-Memory,52/89,三管动态 RAM 芯片(Intel 1103)写,ECE 313 Fall 2006,Lecture 20-Memory,53/89,三管动态 RAM 芯片(Intel 1103)写,ECE 313 Fall 2006,L

26、ecture 20-Memory,54/89,三管动态 RAM 芯片(Intel 1103)写,ECE 313 Fall 2006,Lecture 20-Memory,55/89,三管动态 RAM 芯片(Intel 1103)写,读 写 控 制 电 路,ECE 313 Fall 2006,Lecture 20-Memory,56/89,三管动态 RAM 芯片(Intel 1103)写,读 写 控 制 电 路,ECE 313 Fall 2006,Lecture 20-Memory,57/89,三管动态 RAM 芯片(Intel 1103)写,读 写 控 制 电 路,ECE 313 Fall 20

27、06,Lecture 20-Memory,58/89,存储器与 CPU 的连接-存储器容量的扩展,用 2片 1K 4位 存储芯片组成 1K 8位 的存储器,ECE 313 Fall 2006,Lecture 20-Memory,59/89,(2)字扩展（增加存储字的数量）,用 2片 1K 8位 存储芯片组成 2K 8位 的存储器,ECE 313 Fall 2006,Lecture 20-Memory,60/89,(3)字、位扩展,用 8片 1K 4位 存储芯片组成 4K 8位 的存储器,ECE 313 Fall 2006,Lecture 20-Memory,61/89,存储器与 CPU 的连接

28、的一般步骤,(1)地址线的连接：首选低位地址；,(2)数据线的连接：位数要相等；,(3)读/写线的连接：直接相连；,(4)片选线的连接：MREQ和空闲的高地址组合,(5)合理选用芯片：RAM/ROM分清,(6)其他 时序、负载,Attention:地址线不可悬空，多余的地址线作为控制线，地址线的特定组合决定控制逻辑的设计,ECE 313 Fall 2006,Lecture 20-Memory,62/89,例题：,设CPU有16根地址线，8根数据线，用MREQ（低电平有效）作访存控制信号，用WR作读/写控制信号（高电平为读，低电平为写）。现有如下存储芯片：1Kx4位RAM；4Kx8RAM；8Kx

29、8RAM；2Kx8位ROM；4Kx8ROM；8Kx8ROM，及74L138译码器和各种门电路。请画出CPU与存储器的连接图，要求：1、主存地址空间分配6000H67FFH为系统程序区6800H6BFFH为用户程序区2、合理选用上述芯片，说明各选几片？3、画出存储芯片的片选逻辑图,ECE 313 Fall 2006,Lecture 20-Memory,63/89,(1)写出对应的二进制地址码,(2)确定芯片的数量及类型,A15A14A13 A11 A10 A7 A4 A3 A0,ECE 313 Fall 2006,Lecture 20-Memory,64/89,(3)分配地址线,A10 A0 接

30、 2K 8位 ROM 的地址线,A9 A0 接 1K 4位 RAM 的地址线,(4)确定片选信号,ECE 313 Fall 2006,Lecture 20-Memory,65/89,CPU 与存储器的连接图,ECE 313 Fall 2006,Lecture 20-Memory,66/89,Outline-Memory Systems,OverviewMotivationGeneral Structure and TerminologyMemory TechnologyStatic RAMDynamic RAMCache Memory 3Virtual Memory,ECE 313 Fall

31、2006,Lecture 20-Memory,67/89,CPU,CacheMemory,DRAMMemory,Processor,addr,data,addr,data,Cache Operation,Insert between CPU,Main Mem.Implement with fast Static RAMHolds some of a programs datainstructionsOperation:,ECE 313 Fall 2006,Lecture 20-Memory,68/89,Four Key Cache Questions:,1.Where can block be

32、 placed in cache?(block placement)2.How can block be found in cache?(block identification)3.Which block should be replaced on a miss?(block replacement)4.What happens on a write?(write strategy),ECE 313 Fall 2006,Lecture 20-Memory,69/89,Basic Cache Design,以块的方式组织块的内容标记 tag-extra bits to identify blo

33、ck(part of block address)数据 data-data or instruction words-contiguous memory locations右边的例子:每块一个字(4 byte)Tag为30位Cache中有2个块,CPU,CPU,CPU,tag 0,data 0,CPU,CPU,tag 1,data 1,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,Main Memory,ECE 313 Fall 2006,Lecture 20-Memory,70/89,Cache

34、 Example(2),Assume:r1=0,r2=1,r4=21 cycle for cache access5 cycles for main.mem.access1 cycle for instr.executionAt cycle 1-PC=0 x00Fetch instruction from memorylook in cacheMISS-fetch from main mem(5 cycle penalty),CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:add r1,r1,r2,0 x00000000,0 x000

35、00004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,Main Memory,bne r4,r1,L,sub r1,r1,r1,L:j L,MISS,ECE 313 Fall 2006,Lecture 20-Memory,71/89,Cache Example(3),At cycle 6Execute instr.add r1,r1,r2,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:add r1,r1,r2,0 x00000000,0 x00000004,0 x00000008

36、,0 x0000000C,0 x00000000,b0,b1,Cache,Main Memory,bne r4,r1,L,sub r1,r1,r1,L:j L,CycleAddressOp/Instr.r1,1-5FETCH 0 x000,60 x0add r1,r1,r2 1,ECE 313 Fall 2006,Lecture 20-Memory,72/89,Cache Example(4),At cycle 6-PC=0 x04Fetch instruction from memorylook in cacheMISS-fetch from main mem(5 cycle penalty

37、),CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:add r1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,Main Memory,bne r4,r1,L,sub r1,r1,r1,L:j L,CycleAddressOp/Instr.r1,1-5FETCH 0 x0,60 x0add r1,r1,r2 1,MISS,6-10FETCH 0 x4,ECE 313 Fall 2006,Lecture 20-Memory,73

38、/89,Cache Example(5),At cycle 11Execute instr.bne r4,r1,L,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:add r1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,Main Memory,bne r4,r1,L,sub r1,r1,r1,L:j L,CycleAddressOp/Instr.r1,1-5FETCH 0 x000,60 x0add r1,r1,r2 1,

39、6-10FETCH 0 x004,110 x4bne r4,r1,L 1,ECE 313 Fall 2006,Lecture 20-Memory,74/89,Cache Example(6),At cycle 11-PC=0 x00Fetch instruction from memoryHIT-instruction in cache,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:add r1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,

40、b1,Cache,Main Memory,bne r4,r1,L,sub r1,r1,r1,L:j L,CycleAddressOp/Instr.r1,1-5FETCH 0 x0,60 x0add r1,r1,r2 1,6-10FETCH 0 x4,HIT,110 x4bne r4,r1,L 1,11FETCH 0 x0 1,ECE 313 Fall 2006,Lecture 20-Memory,75/89,Cache Example(7),At cycle 12Execute add r1,r1,2,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(e

41、mpty),L:add r1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,Main Memory,bne r4,r1,L,sub r1,r1,r1,L:j L,CycleAddressOp/Instr.r1,1-5FETCH 0 x0,60 x0add r1,r1,r2 1,6-10FETCH 0 x4,110 x4bne r4,r1,L 1,12FETCH 0 x0 1,12add r1,r1,2 2,ECE 313 Fall 2006,Lecture 20-Memory,76/8

42、9,Cache Example(8),At cycle 12-PC=0 x04Fetch instruction from memoryHIT-instruction in cache,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:add r1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,Main Memory,bne r4,r1,L,sub r1,r1,r1,L:j L,CycleAddressOp/Instr.r1,1

43、-5FETCH 0 x0,60 x0add r1,r1,r2 1,6-10FETCH 0 x4,110 x4bne r4,r1,L 1,12FETCH 0 x0 1,12add r1,r1,2 2,12FETCH 0 x04,HIT,ECE 313 Fall 2006,Lecture 20-Memory,77/89,Cache Example(9),At cycle 13Execute instr.bne r4,r1,LBranch not taken,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:add r1,r1,r2,0 x0

44、0000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,Main Memory,bne r4,r1,L,sub r1,r1,r1,L:j L,CycleAddressOp/Instr.r1,1-5FETCH 0 x0,60 x0add r1,r1,r2 1,6-10FETCH 0 x4,110 x4bne r4,r1,L 1,12FETCH 0 x0 1,12add r1,r1,2 2,12FETCH 0 x04,13bne r4,r1,L,ECE 313 Fall 2006,Lecture 20-Memory,7

45、8/89,Cache Example(10),At cycle 13-PC=0 x08Fetch Instruction from MemoryMISS-not in cache,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:add r1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,Main Memory,bne r4,r1,L,sub r1,r1,r1,L:j L,CycleAddressOp/Instr.r1,1-5F

46、ETCH 0 x0,60 x0add r1,r1,r2 1,6-10FETCH 0 x4,110 x4bne r4,r1,L 1,12FETCH 0 x0 1,12add r1,r1,2 2,12FETCH 0 x04,13bne r4,r1,L,13FETCH 0 x08,MISS,ECE 313 Fall 2006,Lecture 20-Memory,79/89,Cache Example(11),At cycle 17-PC=0 x08Put instruction into cacheReplace existing instruction,CPU,CPU,CPU,(empty),(e

47、mpty),CPU,CPU,(empty),(empty),L:add r1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,Main Memory,bne r4,r1,L,sub r1,r1,r1,L:j L,CycleAddressOp/Instr.r1,1-5FETCH 0 x0,60 x0add r1,r1,r2 1,6-10FETCH 0 x4,110 x4bne r4,r1,L 1,12FETCH 0 x0 1,12add r1,r1,2 2,12FETCH 0 x04,13

48、bne r4,r1,L,13-17FETCH 0 x08,ECE 313 Fall 2006,Lecture 20-Memory,80/89,Cache Example(12),At cycle 18Execute sub r1,r1,r1,CPU,CPU,CPU,(empty),(empty),L:add r1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,Main Memory,bne r4,r1,L,sub r1,r1,r1,L:j L,CycleAddressOp/Instr.

49、r1,1-5FETCH 0 x0,60 x0add r1,r1,r2 1,6-10FETCH 0 x4,110 x4bne r4,r1,L 1,12FETCH 0 x0 1,12add r1,r1,2 2,12FETCH 0 x04 2,13bne r4,r1,L 2,13-17FETCH 0 x08 2,18sub r1,r1,r1 0,ECE 313 Fall 2006,Lecture 20-Memory,81/89,Cache Example(13),At cycle 18Fetch instruction from memoryMISS-not in cache,CPU,CPU,CPU

50、,(empty),(empty),CPU,CPU,(empty),(empty),L:add r1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,Main Memory,bne r4,r1,L,sub r1,r1,r1,L:j L,CycleAddressOp/Instr.r1,1-5FETCH 0 x0,60 x0add r1,r1,r2 1,6-10FETCH 0 x4,110 x4bne r4,r1,L 1,12FETCH 0 x0 1,12add r1,r1,2 2,12FET