VHDL程序设计数字电子表.ppt
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1、第六章 VHDL综合应用,数字电子时钟显示电路,6 个七段数码管,SEGOUT(8),CLR,时钟显示电路方框图,CP,FPGA,SELOUT(6),24进制计数器,60进制计数器,60进制计数器,BCD 七段译码电路,BCD 选择,BCD(8)BIN(6),6 个七段数码管,扫描电路 S(3),SEG(8),NUM(4),BCD(3-0),BCD(7-4),ENB(0),ENB(1),ENB(2),DBH,DBM,DBS,BIN(6),时钟显示电路方框图,SEC,CLR,CYH,CYS,CYM,分频器Q,CP,38译码,24进制计数器,60进制计数器,60进制计数器,BCD 七段译码电路,B
2、CD 选择,BCD(8)BIN(6),6 个七段数码管,扫描电路 S(3),SEG(8),NUM(4),BCD(3-0),BCD(7-4),ENB(0),ENB(1),ENB(2),DBH,DBM,DBS,BIN(6),时钟显示电路方框图,SEC,CLR,CYH,CYS,CYM,分频器Q,CP,38译码,PROCESS(CP)BeginIF CPEvent AND CP=1 thenDLY=Q(21);Q=Q+1;END IF;END PROCESS;,Free_Counter:Block Signal Q:STD_LOGIC_VECTOR(24 DOWNTO 0);Signal DLY:ST
3、D_LOGIC;BeginPROCESS(CP)BeginIF CPEvent AND CP=1 thenDLY=Q(21);Q=Q+1;END IF;END PROCESS;SEC=Q(21)AND NOT DLY;-about 1Hz S=Q(15 DOWNTO 13);-about 250 HzENB=001 WHEN(S=0 OR S=1)ELSE010 WHEN(S=2 OR S=3)ELSE100 WHEN(S=4 OR S=5)ELSE000;BIN=DBS WHEN ENB=001 ELSEDBM WHEN ENB=010 ELSEDBH WHEN ENB=100 ELSE00
4、0000;End Block Free_Counter;,-主文件声明代码COMPONENT COUNTER60PORT(CP:INSTD_LOGIC;BIN:OUTSTD_LOGIC_VECTOR(5 DOWNTO 0);S:INSTD_LOGIC;CLR:IN STD_LOGIC;EC:IN STD_LOGIC;CY60:OUT STD_LOGIC);END COMPONENT;,-子文件定义代码-*LIBRARY IEEE;USE IEEE.STD_LOGIC_UNSIGNED.ALL;-*ENTITY COUNTER60 ISPORT(CP:IN STD_LOGIC;BIN:OUT S
5、TD_LOGIC_VECTOR(5 DOWNTO 0);S:IN STD_LOGIC;CLR:IN STD_LOGIC;EC:IN STD_LOGIC;CY60:OUT STD_LOGIC);END COUNTER60;,-子文件定义代码ARCHITECTURE a OF COUNTER60 ISSIGNAL Q:STD_LOGIC_VECTOR(5 DOWNTO 0);SIGNAL RST,DLY:STD_LOGIC;BEGINPROCESS(CP,RST)BEGINIF RST=1 THENQ=000000;ELSIF CPevent AND CP=1 THENDLY=Q(5);IF EC
6、=1 THENQ=Q+1;END IF;END IF;END PROCESS;CY60=NOT Q(5)AND DLY;RST=1 WHEN Q=60 OR CLR=1 ELSE 0;BIN=Q WHEN S=1 ELSE 000000;END a;,-主文件声明代码COMPONENT COUNTER24PORT(CP:INSTD_LOGIC;BIN:OUTSTD_LOGIC_VECTOR(5 DOWNTO 0);S:INSTD_LOGIC;CLR:IN STD_LOGIC;EC:IN STD_LOGIC;CY60:OUT STD_LOGIC);END COMPONENT;,-子文件定义代码-
7、*LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;-*ENTITY COUNTER24 ISPORT(CP:IN STD_LOGIC;BIN:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);S:IN STD_LOGIC;CLR:IN STD_LOGIC;EC:IN STD_LOGIC;CY24:OUT STD_LOGIC);END COUNTER24;,-子文件定义代码ARCHITECTURE a OF COUNTER24 ISSIGNAL Q:STD_LOGIC_VECTOR(
8、4 DOWNTO 0);SIGNAL RST,DLY:STD_LOGIC;BEGINPROCESS(CP,RST)BEGINIF RST=1 THENQ=00000;ELSIF CPevent AND CP=1 THENDLY=Q(4);IF EC=1 THENQ=Q+1;END IF;END IF;END PROCESS;CY24=NOT Q(4)AND DLY;RST=1 WHEN Q=24 OR CLR=1 ELSE 0;BIN=(0,Binary_BCD:BlockBEGINBCD=00000000 WHEN BIN=0 ELSE00000001 WHEN BIN=1 ELSE0000
9、0010 WHEN BIN=2 ELSE00000011 WHEN BIN=3 ELSE00000100 WHEN BIN=4 ELSE00000101 WHEN BIN=5 ELSE00000110 WHEN BIN=6 ELSE00000111 WHEN BIN=7 ELSE00001000 WHEN BIN=8 ELSE00001001 WHEN BIN=9 ELSE00010000 WHEN BIN=10 ELSE00010001 WHEN BIN=11 ELSE00010010 WHEN BIN=12 ELSE00010011 WHEN BIN=13 ELSE00010100 WHE
10、N BIN=14 ELSE00010101 WHEN BIN=15 ELSE00010110 WHEN BIN=16 ELSE00010111 WHEN BIN=17 ELSE00011000 WHEN BIN=18 ELSE00011001 WHEN BIN=19 ELSE00100000 WHEN BIN=20 ELSE00100001 WHEN BIN=21 ELSE00100010 WHEN BIN=22 ELSE00100011 WHEN BIN=23 ELSE00100100 WHEN BIN=24 ELSE00100101 WHEN BIN=25 ELSE00100110 WHE
11、N BIN=26 ELSE00100111 WHEN BIN=27 ELSE,00101000 WHEN BIN=28 ELSE00101001 WHEN BIN=29 ELSE00110000 WHEN BIN=30 ELSE00110001 WHEN BIN=31 ELSE00110010 WHEN BIN=32 ELSE00110011 WHEN BIN=33 ELSE00110100 WHEN BIN=34 ELSE00110101 WHEN BIN=35 ELSE00110110 WHEN BIN=36 ELSE00110111 WHEN BIN=37 ELSE00111000 WH
12、EN BIN=38 ELSE00111001 WHEN BIN=39 ELSE01000000 WHEN BIN=40 ELSE01000001 WHEN BIN=41 ELSE01000010 WHEN BIN=42 ELSE01000011 WHEN BIN=43 ELSE01000100 WHEN BIN=44 ELSE01000101 WHEN BIN=45 ELSE01000110 WHEN BIN=46 ELSE01000111 WHEN BIN=47 ELSE01001000 WHEN BIN=48 ELSE01001001 WHEN BIN=49 ELSE01010000 WH
13、EN BIN=50 ELSE01010001 WHEN BIN=51 ELSE01010010 WHEN BIN=52 ELSE01010011 WHEN BIN=53 ELSE01010100 WHEN BIN=54 ELSE01010101 WHEN BIN=55 ELSE01010110 WHEN BIN=56 ELSE01010111 WHEN BIN=57 ELSE01011000 WHEN BIN=58 ELSE01011001 WHEN BIN=59 ELSE00000000;END Block Binary_BCD;,SELECT_BCD:BlockBEGINNUM=BCD(3
14、 DOWNTO 0)WHEN(S=0 OR S=2 OR S=4)ELSEBCD(7 DOWNTO 4);End Block SELECT_BCD;,SEVEN_SEGMENT:BlockBegin-gfedcbaSEG=0111111 WHEN NUM=0 ELSE0000110 WHEN NUM=1 ELSE 1011011 WHEN NUM=2 ELSE1001111 WHEN NUM=3 ELSE1100110 WHEN NUM=4 ELSE1101101 WHEN NUM=5 ELSE1111101 WHEN NUM=6 ELSE0000111 WHEN NUM=7 ELSE 111
15、1111 WHEN NUM=8 ELSE1101111 WHEN NUM=9 ELSE1110111 WHEN NUM=10 ELSE1111100 WHEN NUM=11 ELSE0111001 WHEN NUM=12 ELSE1011110 WHEN NUM=13 ELSE1111001 WHEN NUM=14 ELSE1110001 WHEN NUM=15 ELSE0000000;End Block SEVEN_SEGMENT;,延迟与微分电路,用途:将宽脉冲减小为一个时钟周期的脉 冲宽度;消除小于一个周期的脉冲,延迟与微分电路,时序图:,CP,IN,Q1,Q2,OUT,同步计数器电路,
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- 关 键 词:
- VHDL 程序设计 数字 电子表
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