MIPI协议详细介绍.ppt

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1、,MIPI Protocol Introduction,MIPI Development Team 2010-9-2,What is MIPI?,MIPI stands for Mobile Industry Processor Interface MIPI Alliance is a collaboration of mobile industry leaders.Objective to promote open standards for interfaces to mobile application processors.Intends to speed deployment of

2、new services to mobile users by establishing Spec.Board Members in MIPI Alliance Intel,Motorola,Nokia,NXP,Samsung,ST,TI,What is MIPI?,MIPI Alliance Specification for display DCS(Display Command Set)DCS is a standardized command set intended for command mode display modules.DBI,DPI(Display Bus Interf

3、ace,Display Pixel Interface)DBI：Parallel interfaces to display modules having display controllers and frame buffers.DPI：Parallel interfaces to display modules without on-panel display controller or frame buffer.DSI,CSI(Display Serial Interface,Camera Serial Interface)DSI specifies a high-speed seria

4、l interface between a host processor and display module.CSI specifies a high-speed serial interface between a host processor and camera module.D-PHY D-PHY provides the physical layer definition for DSI and CSI.,DSI Layers,DCS spec,DSI spec,D-PHY spec,Outline,D-PHYIntroductionLane Module,State and Li

5、ne levelsOperating ModesEscape ModeSystem Power StatesElectrical CharacteristicsSummary,Introduction for D-PHY,D-PHY describes a source synchronous,high speed,low power,low cost PHYA PHY configuration containsA Clock LaneOne or more Data LanesThree main lane typesUnidirectional Clock LaneUnidirectio

6、nal Data LaneBi-directional Data LaneTransmission ModeLow-Power signaling mode for control purpose：10MHz(max)High-Speed signaling mode for fast-data traffic：80Mbps 1Gbps per LaneD-PHY low-level protocol specifies a minimum data unit of one byteA transmitter shall send data LSB first,MSB last.D-PHY s

7、uited for mobile applicationsDSI：Display Serial InterfaceA clock lane,One to four data lanes.CSI：Camera Serial Interface,Two Data Lane PHY Configuration,Lane Module,PHY consists of D-PHY(Lane Module)D-PHY may containLow-Power Transmitter(LP-TX)Low-Power Receiver(LP-RX)High-Speed Transmitter(HS-TX)Hi

8、gh-Speed Receiver(HS-RX)Low-Power Contention Detector(LP-CD)Three main lane typesUnidirectional Clock LaneMaster：HS-TX,LP-TXSlave：HS-RX,LP-RXUnidirectional Data LaneMaster：HS-TX,LP-TXSlave：HS-RX,LP-RXBi-directional Data LaneMaster,Slave：HS-TX,HS-RX,LP-TX,LP-RX,LP-CD,Universal Lane Module Architectur

9、e,Lane States and Line Levels,The two LP-TXs drive the two Lines of a Lane independently and single-ended.Four possible Low-Power Lane states(LP-00,LP-01,LP-10,LP-11)A HS-TX drives the Lane differentially.Two possible High Speed Lane states(HS-0,HS-1)During HS transmission the LP Receivers observe L

10、P-00 on the LinesLine Levels(typical)LP：01.2VHS：100300mV(Swing：200mV)Lane StatesLP-00,LP-01,LP-10,LP-11HS-0,HS-1,Operating Modes,There are three operating modes in Data LaneEscape mode,High-Speed(Burst)mode and Control modePossible events starting from the Stop State of control modeEscape mode reque

11、st(LP-11LP-10LP-00LP-01LP-00)High-Speed mode request(LP-11LP-01LP-00)Turnaround request(LP-11LP-10LP-00LP-10LP-00),Escape Mode,Escape mode is a special operation for Data Lanes using LP states.With this mode some additional functionality becomes available：LPDT,ULPS,TriggerA Data Lane shall enter Esc

12、ape mode via LP-11LP-10LP-00LP-01LP-00Once Escape mode is entered,the transmitter shall send an 8-bit entry command toindicate the requested action.Escape mode uses Spaced-One-Hot Encoding.means each Mark State is interleaved with a Space State(LP-00).Send Mark-0/1 followed by a Space to transmit a

13、zero-bit/one-bitA Data Lane shall exit Escape mode via LP-10LP-11Ultra-Low Power StateDuring this state,the Lines are in the Space state(LP-00)Exited by means of a Mark-1 state with a length TWAKEUP(1ms)followed by a Stop state.,Escape Mode,Clock Lane Ultra-Low Power State,A Clock Lane shall enter U

14、LPS viaLP-11LP-10LP-00 exited by means of a Mark-1 with a length TWAKEUP followed by a Stop StateLP-10 TWAKEUP LP-11The minimum value of TWAKEUP is 1ms,High-Speed Data Transmission,The action of sending high-speed serial data is called HS transmission or burst.Start-of-TransmissionLP-11LP-01LP-00SoT

15、(0001_1101)HS Data Transmission BurstAll Lanes will start synchronouslyBut may end at different timesThe clock Lane shall be in High-Speed mode,providing a DDR Clock to the Slave sideEnd-of-TransmissionH Toggles differential state immediately after last payload data bit and keeps that state for a ti

16、me THS-TRAIL,High-Speed Clock Transmission,Switching the Clock Lane between Clock Transmission and LP ModeA Clock Lane is a unidirectional Lane from Master to SlaveIn HS mode,the clock Lane provides a low-swing,differential DDR clock signal.the Clock Burst always starts and ends with an HS-0 state.t

17、he Clock Burst always contains an even number of transitions,Summary for D-PHY,Lane Module,Lane State and Line LevelsLane Module：LP-TX,LP-RX,HS-TX,HS-RX,LP-CDLane States：LP-00,LP-01,LP-10,LP-11,HS-0,HS-1Line Levels(typical)：LP：01.2V,HS：100300mV(Swing：200mV)Operating ModesEscape Mode entry procedure：

18、LP-11LP-10LP-00LP-01LP-00Entry Code LPD(10MHz)Escape Mode exit procedure：LP-10LP-11High Speed Mode entry procedure：LP-11LP-01LP-00SoT(00011101)HSD(80Mbps 1Gbps)High Speed Mode exit procedure：EoTLP-11Control Mode-BTA transmission procedure：LP-11LP-10LP-00LP-10LP-00Control Mode-BTA receive procedure：L

19、P-00LP-10LP-11System Power StatesLow-Power mode,High-Speed mode,Ultra-Low Power modeFault DetectionContention Detection(LP-CD),Watchdog Timer,Sequence Error Detection(Error Report)Global Operation Timing ParameterClock Lane Timing,Data Lane TimingOther Timing Initialization,BTA,Wake-Up from ULPSElec

20、trical CharacteristicsHS-RX,LP-RX,LP-TX,LP-CD,Pin characteristic,Clock signal,Data-Clock timingDC and AC characteristic,Outline,DSIIntroductionLane Distributor/Merger ConceptualPacket StructureData Transmission WayProcessor-Sourced PacketsPeripheral-Sourced PacketsReverse-Direction LP TransmissionVi

21、deo ModeSummary,Introduction for DSI,DSI is a Lane-scalable interface for increased performance.One Clock Lane/One to Four Data LanesDSI-compliant peripherals support either of two basic modes of operationCommand Mode(Similar to MPU IF)Data Lane 0：bidirectionalFor returning data,ACK or error report

22、to hostAdditional Data Lanes：unidirectional.Video Mode(Similar to RGB IF)Data Lane 0：bidirectional or unidirectional;Additional Data Lanes：unidirectional.Video data should only be transmitted using HS mode.Transmission ModeHigh-Speed signaling modeLow-Power signaling modeForward/Reverse direction LP

23、 transmissions shall use Data Lane 0 onlyFor returning data,DSI-compliant systems shall only use Data Lane 0 in LP ModePacket TypesShort Packet：4 bytes(fixed length)Long Packet：665541 bytes(variable length),Two Data Lanes HS Transmission Example,Data Transmission Way,Separate Transmissions,Separate

24、Transmissions,KEY:LPS Low Power State SP Short PacketSoT Start of Transmission LgP Long PacketEoT End of Transmission,Short Packet Structure,Packet Header(4 bytes)Data Identifier(DI)*1byte：Contains the Virtual Channel7:6 and Data Type5:0.Packet Data*2byte：Length is fixed at two bytesError Correction

25、 Code(ECC)*1byte：allows single-bit errors to be corrected and 2-bit errors to be detected.Packet SizeFixed length 4 bytesThe first byte of any packet is the DI(Data Identifier)byte.DI7:6：These two bits identify the data as directed to one of four virtual channels.DI5:0：These six bits specify the Dat

26、a Type.,Long Packet Structure,Packet Header(4 bytes)Data Identifier(DI)*1byte：Contains the Virtual Channel7:6 and Data Type5:0.Word Count(WC)*2byte：defines the number of bytes in the Data Payload.Error Correction Code(ECC)*1byte：allows single-bit errors to be corrected and 2-bit errors to be detecte

27、d.Data Payload(065535 bytes)Length=WC bytesPacket Footer(2 bytes)：ChecksumIf the payload has length 0,then the Checksum calculation results in FFFFhIf the Checksum isnt calculated,the Checksum value is 0000hPacket Size4+(065535)+2=6 65541 bytes,Data Types for Processor-sourced Packets,Error Correcti

28、on Code,P7=0 P6=0 P5=D10D11D12D13D14D15D16D17D18D19D21D22D23 P4=D4D5D6D7D8D9D16D17D18D19D20D22D23 P3=D1D2D3D7D8D9D13D14D15D19D20D21D23 P2=D0D2D3D5D6D9D11D12D15D18D20D21D22 P1=D0D1D3D4D6D8D10D12D14D17D20D21D22D23 P0=D0D1D2D4D5D7D10D11D13D16D20D21D22D23,Checksum,unsigned char xx=0 x01,0 x5a,0 x5a,0 x0

29、3,0 x08,0 x2A,0 x00,0 x01,0 x00,0 xF8,0 x00,0 xF6,0 x57,0 x00,0X00,0 xE5;typedef unsigned short U16;typedef unsigned char U8;U16 CRC_test;U16 crc16_update(U16 crc,U8 a);int main()U16 crc,i;crc=0 xFFFF;for(i=0;i1;i+)crc=crc16_update(crc,xxi);CRC_test=crc;,U16 crc16_update(U16 crc,U8 a)int i;crc=a;for

30、(i=0;i 1)0 x8408;else crc=(crc 1);return crc;,Peripheral-to-Processor LP Transmissions,Detailed format descriptionPacket structure for peripheral-to-processor transactions is the same as forthe processor-to-peripheral direction For a single-byte read response,valid data shall be returned in the firs

31、t byte The second byte shall be sent as 00hIf the peripheral does not support Checksum it shall return 0000h,Peripheral-to-Processor LP Transmissions,Peripheral-to-processor transactions are of four basic typesTearing Effect(TE)：trigger message(BAh)Acknowledge：trigger message(84h)Acknowledge and Err

32、or Report：short packet(Data Type is 02h)Response to Read Request：short packet or long packetGeneric Read Response、DCS Read Response（1byte,2byte,multi byte）FeatureBTA shall take place after every peripheral-to-processor transactionMulti-Lane systems shall use Lane 0 for all peripheral-to-processor tr

33、ansmissionsReverse-direction signaling shall only use LP mode of transmission,Video Mode,DSI supports three formats for Video Mode data transmissionNon-Burst Mode with Sync PulsesNon-Burst Mode with Sync EventsBurst Mode,Summary for DSI,DSI is a Lane-scalable interface.One Clock LaneOne to Four Data

34、 LanesTransmission ModeHigh-Speed signaling mode(differential signal)(100mV300mV)Low-Power signaling mode(single-ended signal)(0V1.2V)For returning data,only use Data Lane 0 in LP ModePacket TypesShort Packet：4 bytes(fixed length)Data ID(1byte)+Data0(1byte)+Data1(1byte)+ECC(1byte)Long Packet：665541 bytes(variable length)Packet Header(4 bytes)+Data Payload(065535 bytes)+Packet Footer(2 bytes)Operation ModeCommand Mode(Similar to MPU IF)Video Mode(Similar to RGB IF)Non-Burst Mode with Sync PulsesNon-Burst Mode with Sync EventsBurst Mode,Thank you!,