数字设计课件第六章组合逻辑设计实践.ppt
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1、2023/5/29,1,Chapter 6 Combinational Logic Design Practices,MSI building blocks are the important element of combinational circuits.,2023/5/29,chapter 6,2,本章重点,具备一定功能的通用组合逻辑电路的设计方法及实例掌握常用的MSI的使用方法及功能扩展掌握译码器、MUX实现组合逻辑功能的方法能分析、设计由MSI构建的电路,2023/5/29,chapter 6,3,6.1 Documentation Standard,1.Signal Names
2、and Active LevelsMost signals(signal name)have active level.active high active lowNaming convention surffix“_L”attaching to signal name represent active low level.Like,EN_L、READY_L In logic relation,EN_L=EN,READY_L=READY。,2023/5/29,chapter 6,4,2.Active levels for pins,2023/5/29,chapter 6,5,Exp2:EN=1
3、(active high),data can be transferredEN=0(active low),data can be transferred,EN,CLK,2023/5/29,chapter 6,6,3.bubble-to-bubble logic design,Make the logic circuit easier to understand.Exp:,2023/5/29,chapter 6,7,6.3 Combinational PLDs,1.Programmable logic arrays(PLA)two level“ANDOR”device.Can be progr
4、ammed to realize any sum-of-products logic expression.An nm PLA with p product terms:ninputs moutputs pproduct terms,2023/5/29,chapter 6,8,43 with 6 product terms,AND array,OR array,2023/5/29,chapter 6,9,2023/5/29,chapter 6,10,2.Programmable Array Logic Devices,Fixed OR array,programmable AND arrayB
5、idirectional input/output pins,熔丝型PAL16L8,,Output enable,2023/5/29,chapter 6,11,3.Generic Array Logic Devices(GAL),an innovation of the PAL;can be erased and reprogrammed;,2023/5/29,chapter 6,12,6.4 Decoder,An important type of combinational circuit.,Output code word,decodeer,1-to-1mapping,1-out-of-
6、m code,nm,n-bit,m-bit,2023/5/29,chapter 6,13,1、bianry decoders,input code:n-bitoutput code:2n-bit 2-4 decoder(2-22),I1,I0,Y3,Y2,Y1,Y0,truth table:?,Yi:?,Yi=miY0=I1I0Y1=I1I0Y2=I1I0Y3=I1I0,2-4decoder,One input combination chooses an output port.,2023/5/29,chapter 6,14,2-4 decoder with enable inputYi=E
7、N mi,2023/5/29,chapter 6,15,(2)74139,dual 2-4 decoder,Input code:B(MSB)A(LSB)Also be called address input.Output code:Y3_LY0_L,2023/5/29,chapter 6,16,(3)74138,3-8 decoder,Enable inputEN=G1G2A_LG2B_LInput code:C(MSB)、B、AOutput code:Y0_L Y7_LYi_L=(ENmi),2023/5/29,chapter 6,17,2023/5/29,chapter 6,18,2、
8、realizing combinational circuits with decoder,review:canonical sumDecoder output:Yi_L=(ENmi)when EN=1,Yi_L=mi=Mi add an NAND gate to the decoders output.Exp:(1)F=AB(0、3),F=AB+AB,2023/5/29,chapter 6,19,(2)if a 3-bit number XYZ is odd number,then ODD output 1,else output 0.realize the function with de
9、coder and gates.solution:F=?F=XYZ(1,3,5,7),2023/5/29,chapter 6,20,(3)F=XYZ(0、1、5)解:,2023/5/29,chapter 6,21,3.Cascading binary decoders,How to construct a 4-16、5-32 decoder?use multiple 2-4 or 3-8 decoders to cascade.PS.:confirm the number of decoders according to the input and output bits.only one c
10、hip works in each decoding.,2023/5/29,chapter 6,22,Exp:a 4-16 decoder,Inputs:4-bit N3、N2、N1、N0。Outputs:16-bit DEC15_LDEC0_LNeed 2 3-8 decoders.Use the MSB of the inputs as chip-select bit.,N3 N2 N1 N0,N3 N2 N1 N0,2023/5/29,chapter 6,23,Chip selecting,2023/5/29,chapter 6,24,Exp:4-bit prime-number det
11、ector.Realizing it with 74138 and some gates.,N3,N2,N1,N0,F,2023/5/29,chapter 6,25,4、7-segment decoder,Classify of 7-seg displayer:in materials:LED(发光二极管)LCD(液晶)In working mode:common-cathode(共阴极)common-anode(共阳极),2023/5/29,chapter 6,26,7-segment decoder transform the input BCD code to 7-segment dis
12、playing code.devices:7446A、74LS47(驱动共阳)74LS48、74LS49(驱动共阴),00001001 are useful input codes.10101111 are unused BCD code.,2023/5/29,chapter 6,27,74LS49,2023/5/29,chapter 6,28,5、BCD decoder(二十进制译码器),Inputs:BCD,Y0,Y9,BCD decoder,Output:1-out-of 10 code,2023/5/29,chapter 6,29,5.5 Encoder,1、binary encode
13、r,inputs:,1-out-of-2n code,I0,I1,Im,(m=2n-1),output:,n-bit,Y0,Y1,Yn-1,binary encoder,2023/5/29,chapter 6,30,8-3 encoder,In/out:active high,2023/5/29,chapter 6,31,Y0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I7,2023/5/29,chapter 6,32,2、Priority Encoder,if multiple inputs are asserted,how to deal with?solu
14、tion:assign priority to each input from high to low.let I7 highest priority and decrease from I6 down to I0 A2,A1,A0encode output IDLEwhen no input is asserted,IDLE=1,2023/5/29,chapter 6,33,2023/5/29,chapter 6,34,2023/5/29,chapter 6,35,3、74148 Priority Encoder,EI_L:Enable Input.I7_LI0_L:encode input
15、,I7_L has highest priority.A2_LA0_L:encode outputGS_L:GS_L=0 when one or more of the request inputs are asserted.EO_L:enable output,EO_L=0 when all of the request inputs are negative and EI_L=0.,2023/5/29,chapter 6,36,74148真值表,2023/5/29,chapter 6,37,4、cascading priority encoder,problem:how to constr
16、uct 16-4、32-5 priority encoder?Connecting multiple 8-3 endoder.note:make sure the needed number of chips according to the inputs.need to redesign the output circuit that could produce the correct encoding output.,2023/5/29,chapter 6,38,16-4 priority encoder:use two 74148 U1、U2,U1:input E15_LE8_L;U2:
17、input E7_LE0_L;E15_L is the highest priority,output:A3A0,active high;When one or more inputs is asserted,GS0=1;and A3A0=0000。,U1,U2,2023/5/29,chapter 6,39,思考:若需要编码输出、GS0为低电平有效,如何修改电路输出结构?P.413 figure 6-49 shows the 32-5 priority encoders strcture,.,2023/5/29,chapter 6,40,6.6 Three-state Devices,1、th
18、ree-state buffers,2023/5/29,chapter 6,41,EN_L,A,OUT,EN,EN_L,A,A,OUT_L,OUT_L,Enable means:the buffer output normal logic 0、1 when EN is asserted;the buffer output Hi-Z when EN is negated.,2023/5/29,chapter 6,42,Application,data,返回时序,address of data source,2023/5/29,chapter 6,43,Issues in application
19、TPLZ、TPHZ:time that takes from normal logic into Hi-Z;TPZL、TPZH:time that takes from Hi-Z into normal logic;generally,TPLZ、TPHZ TPZL、TPZH But to confirm the correction in application,a control logic is adopted.,2023/5/29,chapter 6,44,74138的相关引脚信号,查看电路,截止时间(停滞时间),2023/5/29,chapter 6,45,课堂练习,试设计一个电路,当
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