《蒙特卡洛分析》PPT课件.ppt
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1、Monte Carlo simulation for better yield and performance,-A tutorial,start,System requirement,Statistical analysis include process,mismatch effects,Initial design,Design meets the goal?,end,NO,YES,Monte Carlo simulation for better yield and performance,Some design may degrade in performanceOverall de
2、sign yield could be unexpectedly low,If fabrication process parameter and device mismatch effect on same die are not taken in to account then,Hence statistical analysis must find a high place in design cycle,We will perform Monte Carlo analysis on an RF-front end LNA and compare the result if no sta
3、tistical analysis is done.We will also see how to analyze yield and scalar data in Monte Carlo with the help of Low pass filter example.,Monte Carlo simulation,Monte Carlo simulation(example),Linearity,Input matching,Bias N/W,Output matching,Cascode arch.to reduce feedback capacitance,RF-front end(L
4、NA),Knowing System requirement Initial design based on requirement like noise,gain,narrow or wide band.,Monte Carlo simulation,Cadence simulation setup(Normal),Choosing affirma analog artist,2.Choosing Spectre simulator,Choosing model file,which contains all MOS,reg.,cap model parameters.,Monte Carl
5、o simulation,1.Choose setup model libraries,2.Browse and choose model file in the directory,Cadence simulation setup(Normal),Set up analysis(dc,ac,sp etc.),create netlist and run simulator,Monte Carlo simulation,1.Choose analysis to run,2.Choose output to plot,3.Create netlist and run,Cadence simula
6、tion setup(Normal),Plotting results,Monte Carlo simulation,1.Choose direct plot for analysis,2.Click to view the desired result,3.Analyze waveform,Cadence simulation setup(Normal),Monte Carlo modeling in Cadence spectre simulator,Process Section-describes manufacturing parameter,their statistical va
7、riation and a model for device that calculates its(width,length,cap,res.Etc.)according to process parameter.Design-Specific Section designer according to his need can specify Monte Carlo analysis.For example in a current mirror circuit,matched transistors are used and designer can give some correlat
8、ion factor between these matched transistor.,Monte Carlo simulation,Cadence simulation setup(Monte Carlo),Typical Model File,Process Section,All parameter sets to their nominal value,no statistical variation definedModel(NMOSs Rg)is calculated using nominal parameter value,2,1,Monte Carlo simulation
9、,Cadence simulation setup(Monte Carlo),Defining process,mismatch parameter as statistically assigned value,Assesses the device mismatch on different die,which could have gone through some different process parameters during fabrication.,Assesses the device mismatch on same die,which could have gone
10、through some different process parameter.,Variation defined as a distributed function,Monte Carlo simulation,Process Section,Cadence simulation setup(Monte Carlo),Design Specific Section,This includes the circuit connectivity(two resistors,and corresponding current sources that feed them),Defining c
11、orrelation between two devices(R1,R2),Note:Alternatively this information can also be inserted through Artist Monte Carlo Tool.,Monte Carlo simulation,Cadence simulation setup(Monte Carlo),Monte Carlo simulation,Model file used for LNA example,NoteThis is not based on foundry data but modeled for il
12、lustrative purposes.,Cadence simulation setup(Monte Carlo),Monte Carlo simulation,After Initial design that meets the system requirement,statistical analysis must have to be carried out.,Make sure the addition of process and mismatch parameter section in model file.Make certain to include the partic
13、ular section(for exa.Stats in spectre)in simulation model libraryGo to toolMonte Carlo in affirma analog artist,Cadence simulation setup(Monte Carlo),Monte Carlo simulation,Choose no of iteration(default=100),1.Choose which variation to include Processdevice mismatch effect on two diff.die Mismatchd
14、evice mismatch effect on same die,2.Click if you want to see the family of curve i.e.curve from each iteration,3.Define the expressions/signals on which Monte Carlo analysis will be performed.,Note:calculator can also be used to get these expression,Finally run the analysis,Cadence simulation setup(
15、Monte Carlo),Monte Carlo simulation,(Analyzing waveform),Matching,Normal simulation(without statistical variation),Monte Carlo Simulation(with statistical variation),Process parameter and mismatch effect,Input&Output matching N/W,DEGRADES,Overall design performance(noise,gain etc.),DEGRADES,S11,S22,
16、Monte Carlo simulation,(Analyzing waveform),Matching(VSWR):It tells how well input and output N/W are matched.,Monte Carlo simulation,Normal simulation,VSWR1,VSWR2,Variations in VSWR,Monte Carlo simulation,(Analyzing waveform),Matching(forward and reverse transmission gain),It has deteriorated the p
17、erformance significantly,as a minimum S12 and maximum S21 value is desirable.,Normal simulation,Monte Carlo simulation,S12,S21,Monte Carlo simulation,(Analyzing waveform),Normal simulation,Monte Carlo simulation,Stability:A Kf value 1,is desired for an stable amplifier,Kf value has become 1,and cons
18、equently creating a potential unstability,hence a large margin is required at initial design phase.,Stability factor,Monte Carlo simulation,(Analyzing waveform),Normal simulation,Monte Carlo simulation,Noise Performance,As visible,design has a robust noise performance at desired band(2.4-2.5 GHz)BUT
19、.,Noise figure,Periodic Output noise,Monte Carlo simulation,(Analyzing waveform),But LNA as an RF-front end has to provide enough gain with maximum noise suppression to maintain an allowable SNR at demodulators input.,It fails to meet the gain requirement,Gain,Monte Carlo simulation,We will quickly
20、go over another example of low pass filter and see how to analyze scalar data and yield through Monte Carlo simulation,Monte Carlo simulation,Initial Design:Circuit designing according to system requirement,Low-Pass Filter,Monte Carlo simulation,1.Running normal analysis,2.Specifying statistical var
21、iation in model file,3.Running Monte Carlo analysis,1,2,3,Cadence simulation setup(Monte Carlo),Monte Carlo simulation,Simulation shows db20 and phase values are greatly affected by statistical variations introduced in transistor.Hence the need for redesigning the circuit,(Analyzing results),Monte C
22、arlo simulation,(Analyzing Scalar data),1.Choose resultsplot Histogram,2.Choose parameters to plot,3.Analyze the histogram appeared in waveform window,Monte Carlo simulation,1.Choose results specification limits,2.Set bounds and limits,3.Choose Results yield simple in analysis window,4.Set suppressi
23、on value for yield,5.Analyze yield,Only 64%iterations passes the specified limits for bandwidth and ymax,(Analyzing Yield),Monte Carlo simulation(PLL Components),Overview,Reference clock,Detector output,Loop filter response,Oscillator output,Clock divider output,Phase/frequency detector determines t
24、he difference between the phase or frequency of two signals The loop filter removes the high-frequencies from the voltage-controlled oscillator(VCO)controlling voltage The VCO produces and output frequency controlled by a voltage,Monte Carlo simulation(PLL Components),Noise Sources,Detector noise,VC
25、O noise,-Quantization noise,In PLL design it is highly desirable to be able to see the impact of all noise sources,which in turn affects the overall PLL performance.,Due to reference jitter,Due to variation in control voltage,Due to uncertainty involved in discretization,Monte Carlo simulation(VCO),
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