千万不要删！！！！！！！.doc

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1、/* * * file stm32f10x_rcc.c * author MCD Application Team * version V3.3.0 * date 04/16/2010 * brief This file provides all the RCC firmware functions. * * copy * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER

2、 FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WI

3、TH THEIR PRODUCTS. * * © COPYRIGHT 2010 STMicroelectronics */ /* Includes -*/#include stm32f10x_rcc.h/* addtogroup STM32F10x_StdPeriph_Driver * */* defgroup RCC * brief RCC driver modules * */ /* defgroup RCC_Private_TypesDefinitions * */* * */* defgroup RCC_Private_Defines * */* - RCC register

4、s bit address in the alias region - */#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)/* - CR Register -*/* Alias word address of HSION bit */#define CR_OFFSET (RCC_OFFSET + 0x00)#define HSION_BitNumber 0x00#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)/* Alias word addres

5、s of PLLON bit */#define PLLON_BitNumber 0x18#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)#ifdef STM32F10X_CL /* Alias word address of PLL2ON bit */ #define PLL2ON_BitNumber 0x1A #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4) /* Alia

6、s word address of PLL3ON bit */ #define PLL3ON_BitNumber 0x1C #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)#endif /* STM32F10X_CL */ /* Alias word address of CSSON bit */#define CSSON_BitNumber 0x13#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_Bit

7、Number * 4)/* - CFGR Register -*/* Alias word address of USBPRE bit */#define CFGR_OFFSET (RCC_OFFSET + 0x04)#ifndef STM32F10X_CL #define USBPRE_BitNumber 0x16 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)#else #define OTGFSPRE_BitNumber 0x16 #define CFGR_OTGFS

8、PRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)#endif /* STM32F10X_CL */ /* - BDCR Register -*/* Alias word address of RTCEN bit */#define BDCR_OFFSET (RCC_OFFSET + 0x20)#define RTCEN_BitNumber 0x0F#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber *

9、 4)/* Alias word address of BDRST bit */#define BDRST_BitNumber 0x10#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)/* - CSR Register -*/* Alias word address of LSION bit */#define CSR_OFFSET (RCC_OFFSET + 0x24)#define LSION_BitNumber 0x00#define CSR_LSION_BB (PERIP

10、H_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)#ifdef STM32F10X_CL/* - CFGR2 Register -*/ /* Alias word address of I2S2SRC bit */ #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) #define I2S2SRC_BitNumber 0x11 #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4) /*

11、Alias word address of I2S3SRC bit */ #define I2S3SRC_BitNumber 0x12 #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)#endif /* STM32F10X_CL */* - RCC registers bit mask - */* CR register bit mask */#define CR_HSEBYP_Reset (uint32_t)0xFFFBFFFF)#define CR_HSEBYP_

12、Set (uint32_t)0x00040000)#define CR_HSEON_Reset (uint32_t)0xFFFEFFFF)#define CR_HSEON_Set (uint32_t)0x00010000)#define CR_HSITRIM_Mask (uint32_t)0xFFFFFF07)/* CFGR register bit mask */#if defined (STM32F10X_LD_VL) | defined (STM32F10X_MD_VL) | defined (STM32F10X_CL) #define CFGR_PLL_Mask (uint32_t)0

13、xFFC2FFFF)#else #define CFGR_PLL_Mask (uint32_t)0xFFC0FFFF)#endif /* STM32F10X_CL */ #define CFGR_PLLMull_Mask (uint32_t)0x003C0000)#define CFGR_PLLSRC_Mask (uint32_t)0x00010000)#define CFGR_PLLXTPRE_Mask (uint32_t)0x00020000)#define CFGR_SWS_Mask (uint32_t)0x0000000C)#define CFGR_SW_Mask (uint32_t)

14、0xFFFFFFFC)#define CFGR_HPRE_Reset_Mask (uint32_t)0xFFFFFF0F)#define CFGR_HPRE_Set_Mask (uint32_t)0x000000F0)#define CFGR_PPRE1_Reset_Mask (uint32_t)0xFFFFF8FF)#define CFGR_PPRE1_Set_Mask (uint32_t)0x00000700)#define CFGR_PPRE2_Reset_Mask (uint32_t)0xFFFFC7FF)#define CFGR_PPRE2_Set_Mask (uint32_t)0x

15、00003800)#define CFGR_ADCPRE_Reset_Mask (uint32_t)0xFFFF3FFF)#define CFGR_ADCPRE_Set_Mask (uint32_t)0x0000C000)/* CSR register bit mask */#define CSR_RMVF_Set (uint32_t)0x01000000)#if defined (STM32F10X_LD_VL) | defined (STM32F10X_MD_VL) | defined (STM32F10X_CL) /* CFGR2 register bit mask */ #define

16、 CFGR2_PREDIV1SRC (uint32_t)0x00010000) #define CFGR2_PREDIV1 (uint32_t)0x0000000F)#endif#ifdef STM32F10X_CL #define CFGR2_PREDIV2 (uint32_t)0x000000F0) #define CFGR2_PLL2MUL (uint32_t)0x00000F00) #define CFGR2_PLL3MUL (uint32_t)0x0000F000)#endif /* STM32F10X_CL */ /* RCC Flag Mask */#define FLAG_Ma

17、sk (uint8_t)0x1F)#ifndef HSI_Value/* Typical Value of the HSI in Hz */ #define HSI_Value (uint32_t)8000000)#endif /* HSI_Value */* CIR register byte 2 (Bits15:8) base address */#define CIR_BYTE2_ADDRESS (uint32_t)0x40021009)/* CIR register byte 3 (Bits23:16) base address */#define CIR_BYTE3_ADDRESS

18、(uint32_t)0x4002100A)/* CFGR register byte 4 (Bits31:24) base address */#define CFGR_BYTE4_ADDRESS (uint32_t)0x40021007)/* BDCR register base address */#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)#ifndef HSEStartUp_TimeOut/* Time out for HSE start up */ #define HSEStartUp_TimeOut (uint16_t)0x050

19、0)#endif /* HSEStartUp_TimeOut */* * */ /* defgroup RCC_Private_Macros * */ /* * */ /* defgroup RCC_Private_Variables * */ static _I uint8_t APBAHBPrescTable16 = 0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9;static _I uint8_t ADCPrescTable4 = 2, 4, 6, 8;/* * */* defgroup RCC_Private_FunctionPrototy

20、pes * */* * */* defgroup RCC_Private_Functions * */* * brief Resets the RCC clock configuration to the default reset state. * param None * retval None */void RCC_DeInit(void) /* Set HSION bit */ RCC-CR |= (uint32_t)0x00000001; /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */#ifndef STM32F10X_

21、CL RCC-CFGR &= (uint32_t)0xF8FF0000;#else RCC-CFGR &= (uint32_t)0xF0FF0000;#endif /* STM32F10X_CL */ /* Reset HSEON, CSSON and PLLON bits */ RCC-CR &= (uint32_t)0xFEF6FFFF; /* Reset HSEBYP bit */ RCC-CR &= (uint32_t)0xFFFBFFFF; /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC-CFGR &

22、= (uint32_t)0xFF80FFFF;#ifdef STM32F10X_CL /* Reset PLL2ON and PLL3ON bits */ RCC-CR &= (uint32_t)0xEBFFFFFF; /* Disable all interrupts and clear pending bits */ RCC-CIR = 0x00FF0000; /* Reset CFGR2 register */ RCC-CFGR2 = 0x00000000;#elif defined (STM32F10X_LD_VL) | defined (STM32F10X_MD_VL) /* Dis

23、able all interrupts and clear pending bits */ RCC-CIR = 0x009F0000; /* Reset CFGR2 register */ RCC-CFGR2 = 0x00000000; #else /* Disable all interrupts and clear pending bits */ RCC-CIR = 0x009F0000;#endif /* STM32F10X_CL */* * brief Configures the External High Speed oscillator (HSE). * note HSE can

24、 not be stopped if it is used directly or through the PLL as system clock. * param RCC_HSE: specifies the new state of the HSE. * This parameter can be one of the following values: * arg RCC_HSE_OFF: HSE oscillator OFF * arg RCC_HSE_ON: HSE oscillator ON * arg RCC_HSE_Bypass: HSE oscillator bypassed

25、 with external clock * retval None */void RCC_HSEConfig(uint32_t RCC_HSE) /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_HSE); /* Reset HSEON and HSEBYP bits before configuring the HSE -*/ /* Reset HSEON bit */ RCC-CR &= CR_HSEON_Reset; /* Reset HSEBYP bit */ RCC-CR &= CR_HSEBYP_Reset; /* Co

26、nfigure HSE (RCC_HSE_OFF is already covered by the code section above) */ switch(RCC_HSE) case RCC_HSE_ON: /* Set HSEON bit */ RCC-CR |= CR_HSEON_Set; break; case RCC_HSE_Bypass: /* Set HSEBYP and HSEON bits */ RCC-CR |= CR_HSEBYP_Set | CR_HSEON_Set; break; default: break; /* * brief Waits for HSE s

27、tart-up. * param None * retval An ErrorStatus enumuration value: * - SUCCESS: HSE oscillator is stable and ready to use * - ERROR: HSE oscillator not yet ready */ErrorStatus RCC_WaitForHSEStartUp(void) _IO uint32_t StartUpCounter = 0; ErrorStatus status = ERROR; FlagStatus HSEStatus = RESET; /* Wait

28、 till HSE is ready and if Time out is reached exit */ do HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); StartUpCounter+; while(StartUpCounter != HSEStartUp_TimeOut) & (HSEStatus = RESET); if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) status = SUCCESS; else status = ERROR; return (status);/* * br

29、ief Adjusts the Internal High Speed oscillator (HSI) calibration value. * param HSICalibrationValue: specifies the calibration trimming value. * This parameter must be a number between 0 and 0x1F. * retval None */void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) uint32_t tmpreg = 0; /*

30、 Check the parameters */ assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue); tmpreg = RCC-CR; /* Clear HSITRIM4:0 bits */ tmpreg &= CR_HSITRIM_Mask; /* Set the HSITRIM4:0 bits according to HSICalibrationValue value */ tmpreg |= (uint32_t)HSICalibrationValue CR = tmpreg;/* * brief Enables or

31、disables the Internal High Speed oscillator (HSI). * note HSI can not be stopped if it is used directly or through the PLL as system clock. * param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. * retval None */void RCC_HSICmd(FunctionalState NewState) /* Check the paramet

32、ers */ assert_param(IS_FUNCTIONAL_STATE(NewState); *(_IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;/* * brief Configures the PLL clock source and multiplication factor. * note This function must be used only when the PLL is disabled. * param RCC_PLLSource: specifies the PLL entry clock source. *

33、For b STM32_Connectivity_line_devices or b STM32_Value_line_devices, * this parameter can be one of the following values: * arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry * arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry * For b other_S

34、TM32_devices, this parameter can be one of the following values: * arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry * arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry * arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2

35、selected as PLL clock entry * param RCC_PLLMul: specifies the PLL multiplication factor. * For b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:4,9, 6_5 * For b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:2,16 * retval None */void RCC_PLLConfig(uint32

36、_t RCC_PLLSource, uint32_t RCC_PLLMul) uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource); assert_param(IS_RCC_PLL_MUL(RCC_PLLMul); tmpreg = RCC-CFGR; /* Clear PLLSRC, PLLXTPRE and PLLMUL3:0 bits */ tmpreg &= CFGR_PLL_Mask; /* Set the PLL configuration bits

37、 */ tmpreg |= RCC_PLLSource | RCC_PLLMul; /* Store the new value */ RCC-CFGR = tmpreg;/* * brief Enables or disables the PLL. * note The PLL can not be disabled if it is used as system clock. * param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. * retval None */void RCC_P

38、LLCmd(FunctionalState NewState) /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState); *(_IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;#if defined (STM32F10X_LD_VL) | defined (STM32F10X_MD_VL) | defined (STM32F10X_CL)/* * brief Configures the PREDIV1 division factor. * note * - Th

39、is function must be used only when the PLL is disabled. * - This function applies only to STM32 Connectivity line and Value line * devices. * param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. * This parameter can be one of the following values: * arg RCC_PREDIV1_Source_HSE: HSE selected

40、as PREDIV1 clock * arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock * note * For b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE * param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. * This parameter can be RCC_PREDIV1_Divx where x:1,16 * retval

41、None */void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source); assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div); tmpreg = RCC-CFGR2; /* Clear PREDIV13:0 and PREDIV1SRC bits */ tmpreg &= (CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); /* Set the PREDIV1 clock source and division