X5045带4Kb SPI EEPROM 的CPU监控器中英文翻译.doc

《X5045带4Kb SPI EEPROM 的CPU监控器中英文翻译.doc》由会员分享，可在线阅读，更多相关《X5045带4Kb SPI EEPROM 的CPU监控器中英文翻译.doc（12页珍藏版）》请在三一办公上搜索。

1、附 录 英文文献4K X5043/X5045 512 x 8 BitCPU Supervisor with 4K SPI EEPROMDESCRIPTIONThese devices combine four popular functions, Poweron Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces boar

2、d space requirements, and increases reliability.Applying power to the device activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code.The Watchdog Timer provides an independen

3、t protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling t

4、he power.The devices low VCC detection circuitry protects the users system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds ar

5、e available, however, Xicors unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.The memory portion of the device is a CMOS Serial EEPROM array with Xicors block lock protection. The array is int

6、ernally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.The device utilizes Xicors proprietary Direct Writecell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years.FE

7、ATURES Selectable time out watchdog timer Low VCCdetection and reset assertionFive standard reset threshold voltagesRe-program low VCCreset threshold voltageusing special programming sequence.Reset signal valid to VCC= 1V Long battery life with low power consumption50A max standby current, watchdog

8、on10A max standby current, watchdog off2mA max active current during read 2.7V to 5.5V and 4.5V to 5.5V power supplyversions 4Kbits of EEPROM1M write cycle endurance Save critical data with Block LockmemoryProtect 1/4, 1/2, all or none of EEPROM array Built-in inadvertent write protectionWrite enabl

9、e latchWrite protect pin 3.3MHz clock rate Minimize programming time16-byte page write modeSelf-timed write cycle5ms write cycle time (typical) SPI modes (0,0 & 1,1) Available packages8-lead MSOP, 8-lead SOIC, 8-pin PDIP14-lead TSSOPPIN DESCRIPTIONSSerial Output (SO)SO is a push/pull serial data out

10、put pin. During a readcycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.Serial Input (SI)SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of t

11、he serial clock.Serial Clock (SCK)The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the falling edge of the clock input.Chip Select (CS)

12、When CS is high, the X5043/45 is deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X5043/45 will be in the standby power mode. CS low enables the X5043/45, placing it in the active power mode. It should be noted that after power-up, a high

13、 to low transition on CS is required prior to the start of any operation.Write Protect (WP)When WP is low, nonvolatile writes to the X5043/45 are disabled, but the part otherwise functions normally.When WP is held high, all functions, including non volatile writes operate normally. WP going low whil

14、e CS is still low will interrupt a write to the X5043/45. If the internal write cycle has already been initiated, WP going low will have no affect on a write.Reset (RESET, RESET)X5043/45, RESET/RESET is an active low/HIGH,open drain output which goes active whenever VCC falls below the minimum VCCse

15、nse level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET also goes active if the Watchdog timer is enabled and CS remains either high or low longer than the Watchdog time out period. A falling edge of CS will reset the watchdog timer.PRINCIPLES OF OPE

16、RATIONPower On ResetApplication of power to the X5043/X5045 activates a Power On Reset Circuit. This circuit pulls the RESET/RESET pin active. RESET/RESET prevents the system microprocessor from starting to operate with insuf-ficient voltage or prior to stabilization of the oscillator.When VCC excee

17、ds the device VTRIP value for 200ms(nominal) the circuit releases RESET/RESET, allowing the processor to begin executing code.Low Voltage MonitoringDuring operation, the X5043/X5045 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET s

18、ignal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms.Watchdog TimerThe Watchdog Timer circuit monitors the microprocessor ac

19、tivity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent an active RESET/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the Status Reg

20、ister determines the watchdog timer period. The microprocessor can change these watchdog bits. With no microprocessor action, the watchdog timer control bits remain unchanged, even during total power failure.VCC Threshold Reset ProcedureThe X5043/X5045 is shipped with a standard VCCthreshold (VTRIP)

21、 voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X5043/X5045 threshold may be adjusted. The procedure is described below, and uses the ap

22、plication of a high voltage control signal.Setting the VTRIP VoltageThis procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIPis 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current

23、setting, then it is necessary to reset the trip point before setting the new value.To set the new VTRIP voltage, apply the desired VTRIP threshold voltage to the VCC pin and tie the WP pin to the programming voltage VP. Then send a WREN command,followed by a write of Data 00h to address 01h.CS going

24、 HIGH on the write operation initiates the VTRIP programmingsequence. Bring WP LOW to complete the operation.Note:This operation also writes 00h to array address 01h.Resetting the VTRIP VoltageThis procedure is used to set the VTRIP to a “native” voltage level. For example, if the current VTRIP is 4

25、.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value.To reset the VTRIP voltage, apply at least 3V to the VCC pin and tie the WP pin to the programming voltage

26、 VP.Then send a WREN command, followed by a write of Data 00h to address 03h. CS going HIGH on the write operation initiates the VTRIP programming sequence.Bring WP LOW to complete the operation.Note:This operation also writes 00h to array address 03h.SPI Serial MemoryThe memory portion of the devic

27、e is a CMOS Serial EEPROM array with Xicors block lock protection. The array is internally organized as x8 bits. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.The device utilizes Xicors proprietary Direct Write cell, provid

28、ing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years.The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families.The device contains an 8-bit instruction register that controls the opera

29、tion of the device. The instruction code is written to the device via the SI input. There are two write operations that requires only the instruction byte. There are two read operations that use the instruction byte to initiate the output of data. The remainder of the operations require an instructi

30、on byte,an 8-bit address, then data bytes. All instruction,address and data bits are clocked by the SCK input. All instructions (Table 1), addresses and data are transferred MSB first.Clock and Data TimingData input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is

31、 output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. CS must be LOW during the entire operation.Write Enable LatchThe device contains a Write Enable Latch. This latch must be SET before a Wr

32、ite Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch . This latch is automatically reset upon a power-up condition and after the completion of a valid byte, page, or status registerwrite cycle. The latch is also reset if WP is brought LOW.

33、When issuing a WREN, WRDI or RDSR commands, it is not necessary to send a byte address or data.Status RegisterThe Status Register contains four nonvolatile control bits and two volatile status bits. The control bits set the operation of the watchdog timer and the memory block lock protection. The St

34、atus Register is formatted as shown in “Status Register”.Status Register: (Default = 30H)The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a “

35、1”, a nonvolatile write operation is in progress. When set to a “0”, no write is in progress.The Write Enable Latch (WEL) bit indicates the status of the “write enable” latch. When WEL = 1, the latch is set and when WEL = 0 the latch is reset. The WEL bit is a volatile, read only bit. The WREN instr

36、uction sets the WEL bit and the WRDS instruction resets the WEL bit.The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any por

37、tion of the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory.The Watchdog Timer bits, WD0 and WD1, select the Watchdog Time-out Period. These nonvolatile bits are programm

38、ed with the WRSR instruction.Read Status RegisterTo read the Status Register, pull CS low to select the device, then send the 8-bit RDSR instruction. Then the contents of the Status Register are shifted out on the SO line, clocked by CLK. Refer to the Read Status Register Sequence . The Status Regis

39、ter may be read at any time, even during a Write Cycle.Write Status RegisterPrior to any attempt to write data into the status register, the “Write Enable” Latch (WEL) must be set by issuing the WREN instruction . First pull CS LOW, then clock the WREN instruction into the device and pull CS HIGH. T

40、hen bring CS LOW again and enter the WRSR instruction followed by 8 bits of data. These 8 bits of data correspond to the contents of the status register. The operation ends with CS going HIGH. If CS does not go HIGH between WREN and WRSR, the WRSR instruction is ignored.Read Memory ArrayWhen reading

41、 from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 8-bit address. Bit 3 of the READ instruction selects the upper or lower half of the device. After the READ opcode and address are sent, the data stored

42、 in the memory at the selected address is shifted out on the SO line. The data stored in memory at the nextaddress can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the high

43、est address is reached, the address counter rolls over to address $000 allowing the read cycle to be continued indefi-nitely. The read operation is terminated by taking CS high. Refer to the Read EEPROM Array Sequence .Write Memory ArrayPrior to any attempt to write data into the memoryarray, the “W

44、rite Enable” Latch (WEL) must be set by issuing the WREN instruction . First pull CS LOW, then clock the WREN instruction into the device and pull CS HIGH. Then bring CS LOW again and enter the WRITE instruction followed by the 8-bit address and then the data to be written. Bit 3 of the WRITE instru

45、ction contains address bit A8, which selects the upper or lower half of the array. If CS does not go HIGH between WREN and WRITE, the WRITE instruction is ignored.The WRITE operation requires at least 16 clocks. CS must go low and remain low for the duration of the operation. The host may continue t

46、o write up to 16 bytes of data. The only restriction is that the 16 bytes must reside within the same page. A page address begins with address x xxxx 0000 and ends with xxxxx 1111. If the byte address reaches the last byte on the page and the clock continues, the counter will roll back to the first

47、address of the page and overwrite any data that has been previously written.For the write operation (byte or page write) to be completed,CS must be brought HIGH after bit 0 of the last complete data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will n

48、ot be completed .While the write is in progress following a status register or memory array write sequence, the Status Register may be read to check the WIP bit. WIP is HIGH while the nonvolatile write is in progress.OPERATIONAL NOTESThe device powers-up in the following state: The device is in the low power standby state. A HIGH to LOW transition on CS is required to enteran active state and receive an instruction. SO pin is high impedance. The Write Enable Latch is reset. The Flag Bit is reset. Reset Signal is active for tPURST.Data ProtectionThe following circuitry has been included