通信工程毕业设计（论文）外文翻译3000字（全文）含出处作者.doc

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1、The features, schematic and architecture of AT89C51The features of AT89C51 are: Compatible with MCS-51 Products 4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-level Program Memory Lock 128 x 8-bit Internal RAM 32 Pro

2、grammable I/O Lines Two 16-bit Timer/Counters Six Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down ModesDescriptionThe AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level inte

3、rrupt architecture,a full duple ser -ial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counter

4、s,serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil -lator disabling all other chip functions until the next hardware reset.Pin ConfigurationsBlock DiagramPin DescriptionVCC Supply voltage.GND Ground.Port 0 Port 0 is an 8-bit

5、 open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memo

6、ry. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during program verification. External pullups are required during program verification.Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 o

7、utput buffers can sink/so -urce four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the lo

8、w-order address bytes during Flash programming and verification.Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs.

9、 As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL

10、) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to externa

11、l data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals durin Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.Th

12、e Port 3 output buffers can sink/sou -rce four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.RSTReset input. A high on t

13、his pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is

14、emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped duri -ng each access to external DataMemory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit

15、set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing co

16、de from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locat

17、ions starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that requi

18、re 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured fo

19、r use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external c

20、lock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invo

21、ked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resume

22、s program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin whe

23、n Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationNote: C1, C2 = 30 pF 10 pF for Crystals= 40 pF 10 pF for Ceramic Resonator

24、sPower-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware res

25、et. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.A microcomputer interface converts information between two for

26、ms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of con

27、version between the external and internal forms is carried out in a number of steps.An analog-to-digital converter(ADC) is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transduce

28、r does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself.Output interfaces take a similar form, th

29、e obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed f

30、or a digital-to-analog converter(DAC). This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned(usually amplified) to a form suitable for operating an actu

31、ator.The signals used within microcomputer circuits are almost always too small to be connected directly to the “outside world” and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most important tasks facing

32、the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the

33、state of a switch or actuator.To solve real-world problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers information and processes the data, it

34、 must also be able to effect change on some portion of the outside world. These hardware devices, called peripherals, are the CPUs window to the outside.The most basic form of peripheral available on microcontrollers is the general purpose I70 port. Each of the I/O pins can be used as either an inpu

35、t or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zero by using CPU instructions to pin may be viewed

36、 (or read.) by the CPU using program instructions.Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer I/O pins to perform the communication function, which

37、 makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously. A universal asynchronous receiver transmitter (UART) communicates asynchronously with other devices. This type of serial port requires the simplest hardware interface. Only two pins are r

38、equired for bi-directional data transfers. Data is transmitted out of the microcontroller on one pin and data received by the UART on the other pin. Each piece of data transmitted or received by the UART has a start bit, several data bits, and a stop bit. The start and stop bits are used to synchron

39、ize the two devices that communicating. This type of serial interface is used most often when a microcontroller must communicate over fairly long distances. With RS-232 level translators connected to the transmit and received pins, the UART may be used to communicate with personal computers or large

40、r computers. Synchronous transmissions require the use of pin to provide the synchronization pin. In addition to RAM, ROM, and EPROM memory modules, other peripherals commonly appearing on microcontrollers include analog-to-digital converters to convert real-world analog signals into a binary number

41、, and EEPROM memory which can be altered as a program is running and is nonvolatile. Also, a module usually referred to as an integration module is included on the microcontroller to provide address & data bus configuration, certain kinds of system protection, and reset and interrupt control.From: s

42、cience and technology of microcontroller （America）2004,vol 2 ,76-81 AT89C51的特性、原理和结构AT89C51的主要性能参数：与MCS-51产品指令系统完全兼容4k 字节可重擦写FLASH闪速存储器1000次擦写周期全静态操作：0Hz24MHz三级加密程序存储器1288字节内部RAM32个可编程I/O口线2个16位定时/计数器6个中断源可编程串行URAR通道低功耗空闲和掉电模式功能特性概述：AT89C51提供以下标准功能：4k 字节FLASH闪速存储器，128字节内部RAM，32个I/O口线，2个16位定时/计数器，一个5

43、向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89C51降至0Hz的静态逻辑操作，并支持两种可选的节电工作模式。空闲方式体制CPU的工作，但允许RAM，定时/计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器体制工作并禁止其他所有不见工作直到下一个硬件复位。AT89C51方框图 引脚功能说明Vcc：电源电压GND：地P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复用。作为输出口用时，每位能吸收电流的方式驱动8个TTL逻辑门电路，对端口写“1”可作为高阻抗输入端用。在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8

44、位）和数据总线复用，在访问期间激活内部上拉电阻。在Flash编程时，P0口接受指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。P1口：P1是一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作为输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。Flash编程和程序校验期间，P1接受低8位地址。P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通

45、过内部的上拉电阻把端口拉到高电平，此时可作输入口。作为输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。在访问外部程序存储器或16位四肢的外部数据存储器（例如执行MOVX DPTR指令）时，P2口送出高8位地址数据，在访问8位地址的外部数据存储器（例如执行MOVX RI指令）时，P2口线上的内容（也即特殊功能寄存器（SFR）区中R2寄存器的内容），在整个访问期间不改变。Flash编程和程序校验时，P2也接收高位地址和其他控制信号。P3口：P3是一个带有内部上拉电阻的8位双向I/O口，P3的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”

46、，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作为输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。RST：复位输入。当振荡器工作时，RST引脚出现两个机器周期以上高电平将使单片机复位。ALE/PROG：当访问外部程序存储器或数据存储器时，ALE（地址锁存允许）输出脉冲用于锁存地址的低8位字节。即使不访问外部存储器，ALE仍以时钟振荡频率的1/6输出固定的正脉冲信号，因此它可对外输出时钟或用于定时目的。要注意的是，每当访问外部数据存储器时将跳过一个ALE脉冲。对Flash存储器编程期间，该引脚还用于输入编程脉冲（PROG）。如有必要，可通过对特殊功能

47、寄存器（SFR）区中的8EH单元D0位置位，可禁止ALE操作。该位置位后，只有一条MOVX和MOVC指令ALE才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE无效。PSEN：程序存储允许输出是外部程序存储器的读选通型号，当89C51由外部存储器取指令（或数据）时，每个机器周期两次PSEN有效，即输出两个脉冲。在此期间，当访问外部数据存储器，这两次有效的PSEN信号不出现。EA/VPP：外部访问允许。欲使CPU仅访问外部程序存储器（地址为0000HFFFFH），EA端必须保持低电平（接地）。需注意的是：如果加密位LB1被编程，复位时内部会锁存EA端状态。如EA端为高电平（

48、接Vcc端），CPU则执行内部程序存储器中的指令。Flash存储器编程时，该引脚加上+12v的编程允许电源Vpp，当然这必须是该器件使用12v编程电压Vpp。XTAL1：振荡器反相放大器及内部时钟发生器的输入端。XTAL2：振荡器反相放大器的输出端时钟振荡器：89C51中有一个用于构成内部振荡器的高增益反相放大器，引脚XTAL1和XTAL2分别是该放大器的输入端和输出端。这个放大器与作为反馈元件的片外石英晶体或陶瓷谐振器一起构成自激振荡器，振荡电路参见图5。外接石英晶体或陶瓷谐振器及电容C1、C2接在放大器的反馈回路中构成并联振荡电路。对外接电容C1、C2虽没有十分严格的要求，但电容容量的大小会轻微影响振荡频率的高低、振荡器工作的稳定性、起振的难易程度及温度稳定性，如果使用石英晶体，我们推荐电容使用30Pf10 Pf，而如使用陶瓷谐振器建议选择40Pf10 Pf。用户也可以采用外部时钟。采用外部时钟的电路如图5右图所示。这种情况下，外部时钟脉冲接到XTAL1端，即内部时钟发生器的输入端XTAL2则悬空。掉电模式：在掉电模式下，振荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内RAM和特殊功能寄存器的内容在终止掉电模式前被冻结。推出掉电模式的唯一方法是硬件复位，复位后将重新定义全部特殊功能寄存器但不改变RAM中的内容，在