机电自动化专业毕业设计(论文)外文资料翻译.doc

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1、毕业设计(论文)英文资料翻译 学生姓名： 学 号： 1403134332 系 别： 机 电 系 专 业： 自动化 指导教师： 2007 年 5 月 18 日AT89C51（8-bit Micro controller with 4K Bytes Flash）Features Compatible with MCS-51 Products 4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 12 MHz 256 x

2、 8-bit Internal RAM 32 Programmable I/O Lines two 16-bit Timer/Counters five Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down ModesDescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable and erasable read only me

3、mory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 and 80C51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory

4、programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.PinConfigurations The AT89C51 provides the following standard features: 4Kb

5、ytes of Flash, 256 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a six-vector two-level interrupt architecture, a full-duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two sof

6、tware selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset.

7、Pin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 can also be configured to be the multiplexed low or

8、der address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull ups are required during program verification.Port 1Port

9、 1 is an 8-bit bi-directional I/O port with internal pull ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will sour

10、ce current (IIL) because of the internal pull ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes

11、during Flash programming and verification. Port 2Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port

12、2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, Port 2

13、uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verificati

14、on.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled

15、low will source current (IIL) because of the pull ups. Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table. Port 3 also receives some control signals for Flash programming and verification.Port PinAlternate FunctionsP3.0RXD(serial input port)P

16、3.1TXD(serial output port)P3.2INTO(external interrupt 0)P3.3INT1(external interrupt 1)P3.4T0(timer 0 external input)P3.5T1(timer 1 external input)P3.6WR(external data memory write strobe)P3.7RD(external data memory read strobe)RSTReset input. A high on this pin for two machine cycles while the oscil

17、lator is running resets the device.ALE/PROGAddress Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the

18、oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX o

19、r MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C52 is executing code from external program memory, PSEN i

20、s activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Not

21、e, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming when 12-volt programming is selected.XTAL1Input to the inve

22、rting oscillator amplifier and input to theinternal clock operating circuit.XTAL2Output from the inverting oscillat or amplifier.Special Function RegistersA map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Note that not all of the addresses are occ

23、upied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to i

24、nvoke new features. In that case, the reset or inactive values of the new bits will always be 0.Interrupt Registers The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register.Data MemoryThe AT89C51 implements 256 b

25、ytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the add

26、ress mode used in the instruction specifies whether the CPU accesses the upper128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).MOV 0A0H, #dataInstructi

27、ons that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV R0, #dataNote that stack operations are examples of indirect addr

28、essing, so the upper 128 bytes of data RAM are available as stack space.Timer 0 and 1Timer 0 and Timer 1 is a 16-bit Timer/CounterAT89C51 (8位微控制单片机，片内含4K BYTES 可反复擦写存储器)主要性能参数：。与MCS-51产品指令和引脚完全兼容。4K字节可重擦写FLASH闪速存储器。1000次擦写周期。全静态操作：0HZ-12MHZ。256*8字节内部RAM。32个可编程I/O口线。2个16位定时/计数器。5个中断源。可编程串行通道。低功耗空闲和掉电

29、模式AT89C51是美国AMTEL公司生产的低电压，高性能CMOS8位单片机，片内含8KBYTES的可反复擦写的只读程序存储器（EPROM）和256BYTES的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度，非易失性存储技术生产，与标准MCS-51指令系统及8051产品引脚兼容，片内置通用8位中央处理器（CPU）和FLASH存储单元，功能强大AT89C51单片机适合于许多较为复杂控制应用场合。功能特性概述：AT89C51提供以下标准功能：4K字节FLASH闪速存储器，256字节内部RAM， 2个16位定时/计数器，一个6向量两级中断结构，一个全双工串行通信口，片内震荡器及时钟电路

30、。同时，AT89C51可降至0HZ的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时/计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但震荡器停止工作并禁止其他所有部件工作直到下一个硬件复位。 引脚功能说明：。VCC：电源电压。GND：地。P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复用口。作为输出口用时，每位能吸收电流的方式驱动8个TTL逻辑门电路，对端口P0写“1”时，可作为高阻抗输入端用。在访问外部数据存储器或者程序存储器时，这组口线分时转换地址（低8位）和数据总线复用，在访问期间激活内部上拉电阻。在FL

31、ASH编程时，P0口接受指令字节，而在程序校验时，输出指令字节，校验时，要求接上拉电阻。 。P1口： P1是一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉倒高电平，此时可作为输入口，作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流I。FLASH编程和程序校验期间，P1接受低8位地址。P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口P2写“1”，通过内部的上拉电阻把端口拉倒高电平，此时可作为输出口，作

32、为输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（I）。在访问外部程序存储器或16位地址的外部数据存储器（例如执行MOVXDPTR指令）时，P2口送出高8位地址数据。在访问8位地址的外部数据存储器（如执行MOVXRI指令）时，P2口输出P2锁存器的内容。 FLASH编程或校验时，P2接受高位地址和一些控制器。P3口：P3口是一组带有内部上拉电阻的8位双向I/O口。P3口输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对P3口写入“1”时，它们被内部上拉电阻高并可作为输入口。此时，被外部拉低的P3口将用上拉电阻输出电流（I）。 P3口除了作为一般的I/O口线外

33、，更重要的用途是它的第二功能，如下表所示：端口引脚第二功能P3.0RXD(串行输入口)P3.1TXD(串行输出口)P3.2INTO(外中断0)P3.3INT1(外中断1)P3.4T0(定时/计数器0)P3.5T1(定时/计数器1)P3.6WR(外部数据存储器写选通)P3.7RD(外部数据存储器读选通)此外，P3口还接受一些用于FLASH闪速存储器编程和程序校验的控制信号。RST：复位输入。当震荡器工作时，RST引脚出现两个机器周期以上的高电平将使单片机复位。ALE/PROG：当访问外部程序存储器或数据存储器时，ALE（地址锁存允许）输出脉冲用于锁存地址的低8位字节。一般情况下，ALE仍一时钟震

34、荡频率的1/6输出固定的脉冲信号，因为它对外输出时钟或用于定时目的。要注意的是：每个访问外部数据存储器时将跳过一个ALE脉冲。对FLASH存储器编程期间，该引脚还用于输入编程脉冲（PROG）。如有必要，可通过对特殊功能寄存器（SFR）区中的8EH单元的D0位置位，可禁止ALE操作。该位置位后，只有一条MOVX和MOVC指令才能将ALE激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE禁止位无效。PSEN：程序储存允许（PSEN）输出是外部程序存储器的读选通信号，当AT89C52由外部程序存储器取指令（或数据）时，每个机器周期两次PSEN有效，即输出两个脉冲。在次期间，当访问外部

35、数据存储器，将跳过两次PSEN信号。EA/VPP：外部访问允许。欲使CPU仅访问外部程序存储器（地址为0000H-FFFFH），EA端必须保持低电平（接地）。需要注意的是：如果加密位LB1被编程，复位时内部会锁存EA端状态。如EA端高电平（接VCC），CPU则执行内部程序存储器中的指令。FLASH存储器编程时，该引脚加上+12V的编程允许电源VPP，当然这必须是该器件是使用12V编程电压VPP。XTAL1：振荡器反相放大器的及内部时钟发生器的输入端。XTAL2：振荡器反相放大器的输出端。特殊功能寄存器：在AT89C51片内存储器中，80H-FFH共128个单元为特殊功能寄存器（SFE），SFR

36、的地址空间映象如表2所示。并非所有的地址都被定义，从80H-FFH共128个字节只有一部分被定义，还有相当一部分没有定义。对没有定义的单元读写将是无效的，读出的数据将不确定，而写入的数据也将丢失。不应该将数据“1”写入为定义的单元，由于这些单元在将来的产品中可能赋予新的功能，在这种情况下，复位后这些单元数值总是“0”。中断寄存器：AT89C51有5个中断源，2个中断优先级，IE寄存器控制各中断位，IP寄存器中5个中断源的每个可定为2个优先级。数据存储器：AT89C51有256个字节的内部RAM，80H-FFH高128个字节与特殊功能寄存器（SFR）地址是重叠的，也就是高128字节的RAM和特殊功能寄存器的地址是相同的，但物理上他们是分开的。当一条指令访问7EH以上的内部地址单元时，指令中使用的寻址方式不同的，也即寻址方式决定是访问高128字节RAM还是访问特殊功能寄存器。如果指令是直接寻址方式则为访问特殊功能寄存器。例如，下面的直接寻址指令访问特殊功能寄存器。MOV 0A0H，#DATA间接寻址指令访问高128字节RAM，例如，下面的间接寻址指令中，R0的内容为0A0H，则访问数据字节地址为0A0H，而不上一P2口（OAOH）。MOV R0，#DATA堆栈操作也是间接寻址方式，所以，高128位数据RAM也可作为堆栈使用。定时器0和定时器1：定时器0和1是一个16位定时/计数器。