第07讲——故障模拟-超大规模集成电路测试技术ppt课件.ppt

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1、2023/3/19,VLSI Test:Lecture 7,1,Lecture 7 Fault Simulation 第七讲：故障模拟,2023/3/19,VLSI Test:Lecture 7,2,Contents内容目录,Problem and motivationFault simulation algorithmsRandom Fault SamplingSummary,2023/3/19,VLSI Test:Lecture 7,3,1 Problem and Motivation问题和驱动,Fault simulation Problem:GivenA circuitA sequen

2、ce of test vectorsA fault modelDetermineFault coverage-fraction(or percentage)of modeled faults detected by test vectorsSet of undetected faultsMotivationDetermine test quality and in turn product qualityFind undetected fault targets to improve tests,2023/3/19,VLSI Test:Lecture 7,4,1.1 Fault simulat

3、or in a VLSI Design ProcessVLSI设计过程中的故障模拟器,2023/3/19,VLSI Test:Lecture 7,5,1.2 Fault Simulation Scenario故障模拟假定,Circuit model:mixed-levelMostly logic with some switch-level for high-impedance(Z)and bidirectional signalsHigh-level models(memory,etc.)with pin faultsSignal states:logicTwo(0,1)or three(0

4、,1,X)states for purely Boolean logic circuitsFour states(0,1,X,Z)for sequential MOS circuitsTiming:Zero-delay for combinational and synchronous circuitsMostly unit-delay for circuits with feedback,2023/3/19,VLSI Test:Lecture 7,6,1.2 Fault Simulation Scenario(continued)故障模拟假定（续）,Faults:Mostly single

5、stuck-at faultsSometimes stuck-open,transition,and path-delay faults;analog circuit fault simulators are not yet in common useEquivalence fault collapsing of single stuck-at faultsFault-dropping-a fault once detected is dropped from consideration as more vectors are simulated;fault-dropping may be s

6、uppressed for diagnosisFault sampling-a random sample of faults is simulated when the circuit is large,2023/3/19,VLSI Test:Lecture 7,7,2 Fault Simulation Algorithms故障模拟算法,Serial/串行算法Parallel/并行算法Deductive/演绎算法Concurrent/并发算法Differential/差分算法,2023/3/19,VLSI Test:Lecture 7,8,2.1 Serial Algorithm串行算法,A

7、lgorithm:Simulate fault-free circuit and save responses.Repeat following steps for each fault in the fault list:Modify netlist by injecting one faultSimulate modified netlist,vector by vector,comparing responses with saved responsesIf response differs,report fault detection and suspend simulation of

8、 remaining vectorsAdvantages:Easy to implement;needs only a true-value simulator,less memoryMost faults,including analog faults,can be simulated,2023/3/19,VLSI Test:Lecture 7,9,2.1 Serial Algorithm(Cont.)串行算法（续）,Disadvantage:Much repeated computation;CPU time prohibitive for VLSI circuitsAlternative

9、:Simulate many faults together,2023/3/19,VLSI Test:Lecture 7,10,2.2 Parallel Fault Simulation并行故障模拟,Compiled-code method;best with two-states(0,1)Exploits inherent bit-parallelism of logic operations on computer wordsStorage:one word per line for two-state simulationMulti-pass simulation:Each pass s

10、imulates w-1 new faults,where w is the machine word lengthSpeed up over serial method w-1Not suitable for circuits with timing-critical and non-Boolean logic,2023/3/19,VLSI Test:Lecture 7,11,2.2.1 Parallel Fault Sim.Example并行故障模拟实例,2023/3/19,VLSI Test:Lecture 7,12,2.3 Deductive Fault Simulation演绎故障模

11、拟,One-pass simulationEach line k contains a list Lk of faults detectable on k Following true-value simulation of each vector,fault lists of all gate output lines are updated using set-theoretic rules,signal values,and gate input fault listsPO fault lists provide detection dataLimitations:Set-theoret

12、ic rules difficult to derive for non-Boolean gatesGate delays are difficult to use,2023/3/19,VLSI Test:Lecture 7,13,2.3.1 Deductive Fault Sim.Example演绎故障模拟实例,2023/3/19,VLSI Test:Lecture 7,14,2.4 Concurrent Fault Simulation并发故障模拟,Event-driven simulation of fault-free circuit and only those parts of t

13、he faulty circuit that differ in signal states from the fault-free circuit.A list per gate containing copies of the gate from all faulty circuits in which this gate differs.List element contains fault ID,gate input and output values and internal states,if any.All events of fault-free and all faulty

14、circuits are implicitly simulated.Faults can be simulated in any modeling style or detail supported in true-value simulation(offers most flexibility.)Faster than other methods,but uses most memory.,2023/3/19,VLSI Test:Lecture 7,15,2.4.1 Conc.Fault Sim.Example并发故障模拟实例,2023/3/19,VLSI Test:Lecture 7,16

15、,3 Fault Sampling故障采样,A randomly selected subset(sample)of faults is simulated.Measured coverage in the sample is used to estimate fault coverage in the entire circuit.Advantage:Saving in computing resources(CPU time and memory.)Disadvantage:Limited data on undetected faults.,2023/3/19,VLSI Test:Lec

16、ture 7,17,3.1 Motivation for Sampling故障采样的驱动力,Complexity of fault simulation depends on:Number of gatesNumber of faultsNumber of vectorsComplexity of fault simulation with fault sampling depends on:Number of gatesNumber of vectors,2023/3/19,VLSI Test:Lecture 7,18,3.2 Random Sampling Model随机采样模型,2023

17、/3/19,VLSI Test:Lecture 7,19,3.3 Probability Density of Sample Coverage采样故障覆盖率的概率密度,2023/3/19,VLSI Test:Lecture 7,20,3.4 Sampling Error Bounds采样错误限度,C(1-C)|x-C|=3-1/2 Ns,Solving the quadratic equation for C,we get the 3-sigma(99.7%confidence)estimate:,2023/3/19,VLSI Test:Lecture 7,21,4 Summary总结,Fau

18、lt simulator is an essential tool for test development.Concurrent fault simulation algorithm offers the best choice.For restricted class of circuits(combinational and synchronous sequential with only Boolean primitives),differential algorithm can provide better speed and memory efficiency(Section 5.5.6.)For large circuits,the accuracy of random fault sampling only depends on the sample size(1,000 to 2,000 faults)and not on the circuit size.The method has significant advantages in reducing CPU time and memory needs of the simulator.,