CMOS制造工艺流程简介课件.ppt

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1、1,2.1 CMOS制造工艺流程简介,We will describe a modern CMOS process flow.Process described here requires 16 masks and 100 process steps.,第二章 CMOS制备基本流程,2,Stages of IC Fabrication,3,In the simplest CMOS technologies,we need torealize simply NMOS and PMOS transistors for circuits like those illustrated below.,C

2、MOS Digital Gates,反相电路,或非门：同时输入低电平时才能获得高电平输出,4,PMOS and NMOSwafer cross section after fabrication,2-Level Metal CMOS,两层互连布线的CMOS,有源器件（MOS、BJT等类似器件），必须在外加适当的偏置电压情况下，器件才能正常工作。,对于MOS管，有源区分为源区和漏区，在进行互联之前，两者没有差别。,5,Choosing a SubstrateActive RegionN and P WellGateTip or ExtensionSource and DrainContact a

3、nd Local InterconnectMultilevel Metalization,Processing Phases,6,1 m Photoresist,40 nm SiO2,Choose the substrate(type,orientation,resistivity,wafer size),Initial processing:,-Wafer cleaning-thermal oxidation,H2O(40 nm,15 min.900C)-nitride LPCVD(低压化学气相沉积)(80 nm 800C),Substrate selection:-moderately h

4、igh resistivity(25-50 ohm-cm)-(100)orientation-P-type.,80 nm Si3N4,Choosing a Substrate,Si,(100),P Type,2550cm,1st Mask Photoresist spinning and baking 100C(0.5-1.0 m),2.2 有源区的形成,7,Photolithography-Mask#1 pattern alignment and UV exposure-Rinse away non-pattern PR-Dry etch the Nitride layer-Plasma e

5、tch with Fluorine CF4 or NF4 Plasma-Strip Photoresist(H2SO4或O2 plasma),Active Area Definition(主动区),SiO2,Si3N4,Photoresist,8,Wet Oxide(thick SiO2)-H2O(500 nm,90 min.1000C),Strip Nitride layer-Phosophoric acid(磷酸)or plasma etch，选择性问题,Field Oxide Growth,-LOCOS:Local Oxidation of Silicon(局部硅氧化工艺),SiO2,S

6、i3N4,薄的SiO2层，厚的Si3N4层，避免鸟喙(birds beak)的影响,场区:很厚的氧化层，位于芯片上不做晶体管、电极接触的区域，可以起到隔离晶体管的作用。,9,Photolithography(套刻)-Mask#2 pattern alignment and UV exposure,Ion Implantation 离子注入-B+ion bombardment,Penetrate thin SiO2 and field SiO2-反型：半导体表面的少数载流子浓度等于体内的多数载流子浓度时，半导体表面开始反型。-150-200 keV for 1013cm-2-Implantati

7、on Energy and total dose adjusted for depth and concentration,P-well Fabrication,Strip Photoresist,-Rinse away non-pattern PR,2.3 N阱和P阱的形成,SiO2,Photoresist,10,Ion Implantation-P+ion bombardment,-Penetrate thin SiO2 and fieldSiO2-300-400 keV for 1013cm-2-Implantation Energy and,total dose adjusted fo

8、rdepth and concentration,Strip Photoresist,N-well Fabrication,Photolithography-Mask#3 pattern alignment and UV exposure-Rinse away non-pattern PR,11,Thermal Anneal(热退火)-Repair crystal lattice structure damage due to implantation,Dry Furnace(N2 ambient，防止氧化层生成)-Anneal 30 min 800C or RTA(快速热退火)10 sec

9、1000C,-Drive-in 4-6 hours 1000 C-1100 C,Thermal Anneal and Diffusion,N and P Drive-in(扩散推进)-Thermal diffusion of dopant to shallower than desired depth-Drive-in is a cumulative process!,12,Photolithography-Mask#4 pattern alignment and UV exposure-Rinse away non-pattern PR,-B+ion bombardment-50-75keV

10、 for 1-5 1012cm-2,-Implantation Energy andtotal dose adjusted fordepth and concentration,Strip Photoresist,Threshold Adjustment,P-type NMOS,Ion Implantation,2.4 栅电极的制备,开启电压调整,调整之前P阱的掺杂浓度,调整时的注入剂量,13,Threshold Adjustment,N-type PMOS,Photolithography-Mask#5 pattern alignment and UV exposure-Rinse away

11、 non-pattern PR,-As+ion bombardment-75-100keV for 1-5 1012cm-2,-Implantation Energy andtotal dose adjusted fordepth and concentration,Strip Photoresist,Ion Implantation,14,Remove existing gate region oxide,Furnace Steps-Thermal Anneal,-Oxide growth 3-5 nm-O2 ambient-0.5-1 hour 800C,Gate Oxide Growth

12、 栅极氧化层生长,-HF etch，具有良好的选择性,-Dry Furnace(N2 ambient)-30 min 800C,15,LPCVD Deposition of Si-Silane 硅烷,Amorphous or polycrystalline,silicon layer results,Ion Implantation-P+or As+(N+)implant dopesthe poly(typically 5 1015 cm-2),Polysilicon Gate Deposition,0.3-0.5 um,SiO2,多晶硅薄膜,热分解,16,Photolithography-M

13、ask#6 pattern alignment and UV exposure,Plasma Etch-Anisotropic etch 各向异性蚀刻-Vertical etch rate high,-Lateral etch rate low,Gate Patterning（栅极的图形化）,-Rinse away non-pattern PR,Clorine(氯)or Bromine(溴)based for SiO2 selectivity,17,目标：,NMOS器件中的N-注入区,PMOS器件中的P-注入区,多晶硅栅的两侧形成侧壁隔离层的薄氧化层,2.5 前端或延伸区(LDD)的形成,18

14、,LDD:,Lightly Doped Drain(轻掺杂漏)Reduce short channel effects due to gate voltage magnitudes and electric fields Source and Drain must be layered as NMOS:N+N-P or PMOS:P+P-N,Extension(LDD)Formation NMOS,Photolithography-Mask#7 pattern alignment and UV exposure-Rinse away non-pattern PR,-P+ion bombardm

15、ent-50keV for 5 1013cm-2,Strip Photoresist,Ion Implantation,19,Photolithography Mask#8 pattern alignment,and UV exposure Rinse away non-pattern PR Ion Implantation B+ion bombardment 50 keV for 5 1013cm-2,Strip Photoresist,Extension(LDD)Formation PMOS,20,SiO2 隔离介质层,CVD or LPCVD Deposition of SiO2,Sil

16、ane and Oxygen,Or,0.5 um,Provides spacing between gate and source-drain.,SiO2 Spacer Deposition,21,Photolithography,Mask#6 oversized patternalignment and UV exposure Rinse away non-pattern PR,Vertical etch rate high Lateral etch rate low,Strip Photoresist,Anisotropic Spacer Etch,Plasma Etch Anisotro

17、pic etch,Flourine based,22,Screen Oxide Growth Thin SiO2 layer 10 nm to scatter the implanted ions,Photolithography,Mask#9 pattern alignmentand UV exposure Rinse away non-pattern PR,Ion Implantation As+ion bombardment 75 keV for 2-4 1015cm-2,Strip Photoresist,NMOS Source and Drain Implant,2.6 源漏区的形成

18、,Arsenic,Reduce channeling,23,Photolithography,Mask#10 pattern alignmentand UV exposure Rinse away non-pattern PR,Ion Implantation B+ion bombardment 5-10 keV for 1-3 1015cm-2,Strip Photoresist,PMOS Source and Drain Implant,24,N+and P+Drive-in,Thermal diffusion of dopant to shallower than desired dep

19、thDrive-in is a cumulative process!,Dry Furnace(N2 ambient)Anneal 30 min 900C or RTA 60 sec 1000 C-1050 C,Transient Enhanced Diffusion(TED 瞬态增强扩散)Higher than normal diffusivity due to crystal damage,Thermal Annealing,Thermal Anneal Repair crystal lattice structure damage due to implantation,25,2.7 接

20、触与局部互联的形成,Contacts and Interconnects,Titanium sputtering local contacts Conformal Coat with SiO2 Planarization Tungsten Plug vias Aluminum Metal Deposition Repeat Coat Planarize Plug Metal deposition,26,HF etch to remove thin SiO2 Remove screen oxide from drain,source and ploy gate regions Dip(浸)for

21、 a few seconds with HF,Contact Openings,LDD and Sidewall structure NMOS:Lateral N+N-P N-N+PMOS:Lateral P+P-N P-P+,27,Titanium Deposition,Ti is deposited by sputtering(typically 100 nm).Ti target hit with Ar+ions in a vacuum chamber,The Ti is reacted in an N2 ambient,Forms TiSi2 and TiN(typically 1 m

22、in 600-700 C).,TiSi2 has excellent contact characteristics(良好的导体)TiN does not,but can be used for local wiring(导电材料，短程互连布线),TiSi2,TiN,28,Photolithography Mask#11 pattern alignment and UV exposure Rinse away non-pattern PR,TiN etch NH4OH:H2O2:H2O(1:1:5),Strip Photoresist,Local TiN Interconnect,Therma

23、l Treat in Ar 减小电阻 1 min 800 C,用TiN作为局部互连引线,29,Conformal layer of SiO2 is deposited by CVD or LPCVD(typically 1 m),PSG(磷硅玻璃)or BPSG(硼磷硅玻璃)磷：Surface passivation(表面钝化)硼：Glass reflow for partial planarization(加热，令表面平整),Chemical Mechanical Polishing(CMP 化学机械抛光),Planarize the wafer surface 平坦化,Polish wit

24、h high pH silica slurry(硅酸盐研磨浆料),Conformal Coat and Planarize,2.8 多层金属互连的形成,SiO2,表面不平坦带来很多问题,两种解决方法：,30,Photolithography Mask#12 pattern alignment and UV exposure,Rinse away non-pattern PR,SiO2 plasma etch Anisotropic etch,Strip Photoresist,Vias to 1st Metal,选择第一层金属布线需要与下层器件结构形成连接的接触孔位置,接触孔形成,31,Via

25、 Deposition Tungsten Plugs(插头),TiN or Ti/TiN barrier layer 粘结层/阻挡层，增强金属与SiO2的粘附性,Sputtering or CVD(few tens of nm),CVD Tungsten(W),Chemical Mechanical Polishing(CMP),Planarize the wafer surface Polish with high pH silica slurry,32,Etch Contact Holes(接触孔的蚀刻)or Line Trenches(沟道)Fill etched regions(蚀刻区

26、的填充)Planarize(平坦化)CMP process Also removes material that“overflowed holes or trenches”,Damascene Process 大马士革镶嵌工艺,大马士革镶嵌工艺包括：,33,Strip Photoresist,Metal#1 Deposition,第一层金属布线,Photolithography Mask#13 pattern alignment and UV exposure Rinse away non-pattern PR,Anisotropic plasma etch,SiO2,Al,光刻胶,Sputt

27、ered Aluminum Al with small amounts of Si and Cu-Cu reduces electromigration 避免电迁移现象带来的断路-Si 降低接触电阻,34,Multiple Metal Layers,Deposits Oxide Layer CMP Photolithography Mask#14 Etch Vias Deposit via material CMP Deposit Next Metal Layer Photolithography Mask#15,Final passivation layer of Si3N4 is depo

28、sited by PECVD and patterned with Mask#16.防止Na+、K+污染和封装中的机械损伤,Final anneal and alloy in forming gas(10%H2 in N2)30min 400-450 C 形成良好的欧姆接触，降低Si/SiO2界面的电荷,SiO2,W,TiN,Si3N4或SiO2,35,Intel processor chip,52MB SRAM chips on a 12”wafer,Photos of state-of-the-art CMOS chips(from Intel website).90 nm technol

29、ogy.,36,Summary of Key ideas,This chapter serves as an introduction to CMOS technology.,It provides a perspective on how individual technologies like oxidation and ion implantation are actually used.,There are many variations on CMOS process flows used in industry.,The process described here is inte

30、nded to be representative,although it is simplified compared to many current process flows.,Perhaps the most important point is that while individual process steps like oxidation and ion implantation are usually studied as isolated technologies,their actual use is complicated by the fact that IC man

31、ufacturing consists of many sequential steps,each of which must integrate together to make the whole process flow work in manufacturing.,37,作业：MEMS 器件制备,最早的MEMS执行器之一：静电驱动的微马达,1、想要体面生活，又觉得打拼辛苦；想要健康身体，又无法坚持运动。人最失败的，莫过于对自己不负责任，连答应自己的事都办不到，又何必抱怨这个世界都和你作对？人生的道理很简单，你想要什么，就去付出足够的努力。2、时间是最公平的，活一天就拥有24小时，差别只

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