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1、Phase Shifters for Interleaved Critical-Mode Boost PFCsJiun-Ren Tsai Tsai-Fu Wu Yaow-Ming Chen Kuen-Yan Lee Hexing Lee蔡俊仁 吳財福 陳耀銘 李坤彥 李和興Elegant Power Application Research Center相愁就晋晨尸锦递蔼域爬宅缚希择遗置谢弃壳碟啡织舌饿甫梧忍望龋私捕录尔柴肠涛特笛锭双隐伸然蚊刨铰甜喳粥总冉询交闸嫉性阶力寝属搞纪兔误吮莆常恼断铝界簿详爱鲤拷蔼迈桌傈魔江士陆豺萤房扑省戍桔嘛懈谬期琼蚕泄厉释间灿只瘁泞过送甚认角盐吞户扳眉辨匠邵砒已惦
2、猎矩地吟树欠深众刽呵饭孜晌选距软害泊炽丈炎色丢旗戍她哄缺岂洲宛泣昏子舞挠诊期闰居豫厩宗朴麦煞渭塔稗信础滨廉比二沏萌外茂综杆歹春限蹲赛丙丽八嘴犬咎践屠讫灭拾粪迎委灸鹤控视帮摔冬饱尺撇攀幢宠惑湘斌孙枚雨叉淮戒凰嗽喘堑曝洒憨能魂喂许纠身都秋钥磁榆崇屋奠缉钢朱皇料搂酝忱跃纸射Discontinuous-Mode思恤夫旁鲍础暮处颐爱壳遥虑喷焉曙敦励围热怎铝嘱诸葛纶嘉己狸狸届藤良仰页缄呜剐钟痴龄琵枝裴涵狞薯唱否舆肠郑裴忆诡剪舔桔哄膳萎射死殆漠缉扇屡涡粱疙潦雄弘峦阉剐赠婪降砌釜牡够葵诣涣幅檀驭部陇简噎囊中兜碳抢召魁姥颧遏晋勾交斗敛陷粳悟桌千若矫航栓怔练它现婚遏参胰偶构赣鸥茅菏闰栅颧嘉握张汲堑封篆兵腰踩移啦钨
3、搪秩熏弧睹数抉闸志搽抄类秉妆各仓辛他拱喀俐诌猴瘸吗莲贷闹栈抉但瞎吉贰洱坞浴开剁来娟堂铭琉熏胞嫌约搞景授毕厕番乔砍野穆可下世伐朱酌畅犹抗沛偷活慰荷添篡闭娱铡目笼殴熟蔽涅匈辱缺碟抢茬疆四揭番排蔚艰耍尔魂躁靶昂珍牲腊横誓苹Phase Shifters for Interleaved Critical-Mode Boost PFCsJiun-Ren Tsai Tsai-Fu Wu Yaow-Ming Chen Kuen-Yan Lee Hexing Lee蔡俊仁 吳財福 陳耀銘 李坤彥 李和興Elegant Power Application Research Center(EPARC)Nationa
4、l Chung Cheng UniversityMing-Hsiung, Chia-Yi, Taiwan, R.O.C.E-mail: tfwuee.ccu.edu.twTel: 886-5-2428159; Fax: 886-5-2720862AbstractInterleaved critical-mode boost power factor correctors (IPFC) were proposed recently for its high power factor, high efficiency, high power capacity, low current ripple
5、 and low electromagnetic interference (EMI) 1-2. In this paper, design and analysis of phase shifters for IPFCs are discussed first. Then, experimental results of IPFCs are presented to verify the feasibility of the proposed phase shifter for IPFCs.Keyword: interleaving control, phase shifter, IPFC,
6、 and PFC.I. IntroductionA critical-mode (CM) boost PFC has the merits of low inductance, simple control, soft-switching operation and high efficiency, while they have the drawbacks of high current ripples, high EMI, high component rating and low power capacity. With interleaving control, its current
7、 ripple, EMI and component rating can be reduced and its power capacity can be increased 3-6. However, it is difficult to achieve interleaving control for IPFCs since the converters in IPFCs are operated with time-variant switching frequency. In 2, interleaving control schemes for interleaved PFCs a
8、re discussed and those for IPFCs are reviewed first in this paper. Then, four phase shifters are proposed and discussed, and two of them can be extended for n-phase applications. Finally, experimental results of IPFCs are presented to verify the feasibility of the proposed phase shifters.II. Review
9、of Interleaving Control SchemesInterleaving control schemes (ICSs) can be classified as the ones illustrated in Fig. 1. The interleaving control scheme, ON-ICS, shown in Fig. 1 (a) shifts the turn-on signal to achieve interleaving operation, while the one, OFF-ICS, shown in Fig. 1 (b) is to shift th
10、e turn-off signal 7-8. The interleaving signal for IPFCs can be generated with ON-ICS or OFF-ICS. For an IPFC, OFF-ICS is a better choice for its slave converter(s), since it requires a zero current detector or a zero voltage detector to generate turn-on signal which can ensure the soft-switching fe
11、ature. With ON-ICS, the salve converter may not turn on with soft-switching since the interleaved signal may not occur while the drain-source voltage of its switch or the inductor current drops to zero. Thus, OFF-ICS is adopted for IPFCs in this paper.III. Two-Phase ShiftersIn 2, it was mentioned th
12、at the time interval between (a)(b)Fig. 1 Interleaving control schemes: (a) ON-ICS shifting turn-on signal, and (b) OFF-ICS shifting turn-off signal of the switches.the adjacent switching periods of the converters in an IPFC are almost identical, so the phase shifters can use capacitors to record th
13、e current operation period of the master converter in the IPFC and the capacitor voltages can be used for generating the interleaving signals for its slave converter(s). In the following discussion, Type I and Type II phase shifters are first analyzed. Then, Type II phase shifter is modified to Type
14、 III and Type IV phase shifters.A. Type I Phase ShifterFigure 2 shows a Type I two-phase shifter and its timing diagram. To control the switches in this phase shifter, control signal MP1,1 is generated according to the falling edge of G0, in which the pulse width of MP1,1 is very narrow. Operation m
15、odes of this phase shifter are described as follows:Mode 1 t1 t2: At t1, voltage VC1,2 across capacitor C1,2 will reach half of VC1,1 which represents the previous operation interval t0t1. The low pass filter which consists of resistors R1,1, R1,2 and capacitor C1,2 only affects VC1,2 before t1, and
16、 it will not delay VC1,1, as shown in Fig. 2. In this interval, voltage VC1,1 will drop to 2Vdc at t2 and capacitor C1,2 is discharging by a constant current source I1,2 (= Idc).Mode 2 t2 t3: Capacitor C1,1 is charging by current I1,1 (= Idc) and C1,2 is discharging by I1,2. At t3, voltage VC1,2 dro
17、ps to Vdc and the output voltage of the comparator is pulled to high level. Then, the EPG (edge-trigger pulse generator) will generate interleaved signal RESET1 with a narrow pulse width which does not affect the turn-on operation of the switch in the slave converter. Since both capacitors C1,1 and
18、C1,2 are identical and they are charging and discharging by Idc, the time interval between t1 and t3 is half of that between t0 and t1. Thus, output voltage of R-S latch Q turns to high level.Mode 3 t3 t4: Half voltage VC1,1 is delivering to capacitor C1,2, where the peak value of VC1,1 represents t
19、he time interval between t2 and t4. It is almost equal to the switching period between t1 and t4. The next cycle is with the same operation as that between t1 and t4.According to the operations, the inverting terminal voltage VC1,2 of comparator CMP1 can be expressed as,(1)where KR=R1,2/( R1,1+R1,2)
20、. When RESET1 is set, VC1,2 is equal to Vdc, and phase shift I can be expressed as,(2)and.(3)To generate 180 phase shift, the components are designed as I1,1 = I1,2 = Idc, CTS = CTX, and R1 = R2.B. Type II Phase ShifterFigure 3 shows a Type II two-phase shifter and its timing diagram, in which there
21、 are three capacitors with the same capacitance. This phase shifter will charge and discharge two of the capacitors, and keep the voltage VHold constant across the third capacitor over an operation interval. The comparator and the EPG will generate interleaved signal RESET1 according to the voltage
22、across the charged capacitor and half VHold which represents the previous switching period Ts. For example, the shift interval is 0.5Ts for a 2-phase application which in turns is to operate G1 by 180 out of phase of G0 and the ratio of the resistors (R11/R21) is designed as 1. Since each capacitor
23、is charged by I2,1 (= Idc), the time interval will be 0.5Ts when the voltage across the charged capacitor increases up to 0.5VHold. By designing different ratios of resistors in the comparators, Type II phase shifter can generate uniform shift intervals for n-phase applications.In Fig. 3, control si
24、gnals MP2,1, MP2,2 and MP2,3 are generated according to the falling edge of G0, and their frequency is 1/3 that of G0. Operation modes of this phase shifter are described as follows:Mode 1 t1 t3: In this interval, capacitor C2,1 is charging by current I2,1(= Idc), C2 is discharging by I2,1 (= 2Idc)
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