MentorSystemCverification.ppt
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1、SystemC Support in ModelSim,1,Advanced Functional Verification using SystemCPresented By:Raghu ArdeisharTechnical Marketing EngineerDesign Verification and Test,ModelSim,SystemC Support in ModelSim,2,Technology OverviewBasic SystemCSCV(SystemC Verification Library)SystemC Support in ModelSimDemo,Age
2、nda,SystemC Support in ModelSim,3,What Is SystemC?,High Level Hardware Verification LanguageModels Designs at High Level of Abstraction(Algorithmic)Designs Modeled in Untimed Manner for Fast ExecutionIdeal for Proof of Concept&Architectural ExplorationBased on C+Matured Language,Well Known to System
3、s DesignersNaturally Interface with Existing C+ModelsStandard C+Development Tools SupportedC+Class Library to Enable System Level&Hardware ModelingConcurrency,Data Types,Timed Events,Interfaces,etc.Modules,Processes,Communications through Ports&Signals,etc.,SystemC Support in ModelSim,4,Technology O
4、verviewBasic SystemCSCVSystemC Support in ModelSimDemo,Agenda,SystemC Support in ModelSim,5,Modules,Interfaces,Ports,Channels,Processes,Events,A SystemC“System”,Port,Interface,Event,Channel,Module Instance,Module Instance,Process,Process,Process,Module,SystemC Support in ModelSim,6,Used to Partition
5、 DesignsMay ContainPortsProcessesInternal Data&ChannelsOther Modules(Hierarchical)Constructor(to Create&Initialize Module)Module-Module Communication via ChannelsModule-Process Communication via Channels,Modules,SC_MODULE(Adder)/ports,processes,internal data,etc.SC_CTOR(Adder)/body of constructor/pr
6、ocess declaration,sensitivities,etc.;,SC_MODULE(Adder).;is a SystemC macro forclass Adder:public sc_module.;,SystemC Support in ModelSim,7,Define Set of Methods(Functions)Method Signatures OnlyNot Implementation of MethodsChannels Implement InterfacesDifferent Implementation for Same Interface Possi
7、bleDerived from SystemC Base Class sc_interfaceBuilt-In Interface Examples:sc_signal_in_if,sc_fifo_in_if,etc.,Interfaces,class simple_rw_if:public sc_interface public:void read(unsigned addr,char*data);void write(unsigned addr,char*data);,SystemC Support in ModelSim,8,Used by Modules to Communicate
8、with SurroundingsAccess Channels through InterfacesWhat a port can do(read,write,etc.)is restricted to the methods defined in the associated interface(s)Ports can only be used with Channels that implement the associated interfacesDerived from SystemC Base Class sc_portUsage:sc_port port_name;,Ports,
9、sc_in a;is a short-hand forsc_port a;a is an input port of type int that can access methods defined in sc_signal_in_if.,SC_MODULE(Adder)sc_in a;sc_in b;sc_out c;/processes,etc.SC_CTOR(Adder)/body of constructor/process declaration,sensitivities,etc.;,SystemC Support in ModelSim,9,Used to Store Ports
10、 are bound to Channels through Interfaces,Channels,SystemC Support in ModelSim,10,Interfaces,Ports,Channels,Port a,Interface a_if,method_c()method_d(),method_c()Implementationmethod_d()Implementation,Port b,Interface b_if,method_e()method_f(),method_e()Implementationmethod_f()Implementation,Module,P
11、ort,Interface,Channel,Channel channel_a,Channel channel_b,a-method_c()Legala-method_f()Illegal,SystemC Support in ModelSim,11,Functions to Describe Module Functionality ConcurrentlyNot HierarchicalConstructor Used to Register Member Functions as SystemC Processes(SC_METHOD,SC_THREAD)Invoked Based on
12、 Static&Dynamic SensitivityProcess-Process Communication via Channels&Events,Processes,SC_MODULE(Adder)sc_in a;sc_in b;sc_out c;void compute()c=a+b;SC_CTOR(Adder)SC_METHOD(compute);sensitive a b;,SystemC Support in ModelSim,12,Always Execute Function Body from Start to EndNo Suspension(No wait()insi
13、de SC_METHODSupport Static SensitivityExecute When Signals on Sensitivity List ChangeExample:sensitive a b;Support Dynamic Sensitivity with next_trigger()Execution continues to the end&return control back to the kernelNext time the method process will be invoked only when the event specified by next
14、_trigger()occursUntil such event occurs,the static sensitivity list is temporarily disabled,Method Processes(SC_METHOD),next_trigger(e1);next_trigger(e1|e2);next_trigger(e1,SystemC Support in ModelSim,13,May Suspend Execution with wait()Statements are executed until wait()is encounteredAt wait(),pro
15、cess execution is suspended until an event it is sensitive to occursContinue to execute from where it was suspendedSupport Static SensitivityExecute When Signals on Sensitivity List ChangeExample:sensitive a b;Support Dynamic Sensitivity with wait(),Thread Processes(SC_THREAD),wait(e1);wait(e1|e2);w
16、ait(e1,SC_MODULE(Adder)sc_in a;sc_in b;sc_out c;void compute()while(1)wait(100,SC_PS);c=a+b;SC_CTOR(Adder)SC_THREAD(compute);sensitive a b;,SystemC Support in ModelSim,14,Basic Synchronization Objects of Class sc_eventUsed to Synchronize causes e1 to be made immediately ready to run,Events,SystemC S
17、upport in ModelSim,15,Immediate NotificationCauses processes which are sensitive to the event to be made immediately ready to runExample:e1.notify();/current delta cycleDelayed NotificationCauses processes which are sensitive to the event to be made immediately ready to run in the next evaluation ph
18、ase(a delta cycle later)Example:e1.notify(SC_ZERO_TIME);/next delta cycleTimed NotificationCauses processes which are sensitive to the event to be made immediately ready to run at a specified time in the futureExample:e1.notify(10,SC_NS);/10ns delay,Events,SystemC Support in ModelSim,16,Turn off Pro
19、cess ImitializationUse dont_initialize()after its SC_METHOD or SC_THREAD declaration inside the constructorGenerate Clock SignalsE.g:sc_clock clk(clk,10,SC_NS,0.2,5,SC_NS,false);Default Period=1ns,Duty Cycle=50%,Initial Value=TrueStart SimulationOSCI Uses sc_start(10,SC_PS);Use run Command in ModelS
20、imStop SimulationExample:sc_stop();,Simulation Control,SystemC Support in ModelSim,17,Supported Formats:VCD(Value Change Dump)WIF(Waveform Interchange Format)ISDB(Integrated Signal Data Base)Step 1:Create Trace FileSyntax:sc_trace_file*=sc_create_trace_file();Step 2:Specify Signals to SaveSyntax:sc_
21、trace(,);Step 3:Close FileVCD:sc_close_vcd_trace_file();WIF:sc_close_wif_trace_file();ISDB:sc_close_isdb_trace_file();,Waveform Export,sc_trace_file*tf=sc_create_vcd_trace_file(myvcd);sc_trace(tf,clock,clock);sc_trace(tf,reset,reset);sc_close_vcd_trace_file(tf);,SystemC Support in ModelSim,18,Techno
22、logy OverviewBasic SystemCTestBench AutomationSCV(SystemC Verification Library)SystemC Support in ModelSimDemo,Agenda,SystemC Support in ModelSim,19,Scaffolding around the designAll the stuff you need to build and verify a designSoftwareProgramming-centric view of the intentSpecified in the verifica
23、tion planCan cost as much or more than the design itselfEfficiency,Reuse,etc are important,TBA is All About Infrastructure,Verification Engineers,SystemC Support in ModelSim,20,Building Infrastructures,Collections of verification componentsComponents that participate in the simulation,but are not pa
24、rt of the designBuild reusable modular componentsto the extent possible,SystemC Support in ModelSim,21,Building a Testbench,DUT,Scoreboard,Test,Basics,Intent is captured in test and scoreboard,SystemC Support in ModelSim,22,Generate more efficient verification reduce time per testObject-Oriented Pro
25、grammingObjects,Abstraction,Encapsulation,Inheritance,etc.Reusable test componentsAutomated stimulus generationConstrained sequence,control and data randomization.Test bench infrastructureSampling of stable test valuesClean interface between SystemC and HDL,SystemC Testbench Automation,SystemC Suppo
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