ARMAssemblylanguageprogramming.ppt

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1、ARM Assembly language programming,AgendaARM Data processing instructionsARM Data transfer instructionsArm Control flow instructionsFeatures of Thumb state,ARM uses three types of instructionsData processing instructions(arithmetic operations,logical operations,register moves,comparisons,shift operat

2、ions).Data transfer(register load/store instructions).Control flow instructions(branch instructions).,Data processing instructions Rules apply to ARM data processing instructions:-All operands are 32 bit s,come either from registers or aas specified as constants in the instruction itself-The result

3、is also 32 bits and is placed in a register.-3 operands are used:2 for inputs and 1 for result.Ex.:ADD r0,r1,r2;r0=r1+r2 Works for both unsigned and 2s complement signed numbers.This may produce carry out signal and overflow bits,but ignored by default Result register can be same as an input operand

4、 register.,Data processing instructions(contd)ARMs basic arithmetic operations:,ADD r0,r1,r2;r0=r1+r2ADC r0,r1,r2;r0=r1+r2+CSUB r0,r1,r2;r0=r1 r2 SBC r0,r1,r2;r0=r1 r2+c+1RSB r0,r1,r2;r0=r2 r2RSC r0,r1,r2;r0=r2 r1+c-1,RSB stands for reverse subtraction.Operands may be unsigned or 2s complement integ

5、ers.C is the carry bit in the CPSR,Data processing instructions(contd)ARMs bit-wise logical operations:,AND r0,r1,r2;r0=r1 and r2(bit-by-bit for 32 bits)ORR r0,r1,r2;r0=r1 or r2 EOR r0,r1,r2;r0 r1 xor r2BIC r0,r1,r2;r0=r1 and not r2,BIC stands for bit clear,where every 1 in the second operand clears

6、 the corresponding bit in the first:,r1:0101 0011 1010 1111 1101 1010 0110 1011r2:1111 1111 1111 1111 0000 0000 0000 0000r0:0000 0000 0000 0000 1101 1010 0110 1011,Data processing instructions(contd)ARMs register move operations:,MOV r0,r2;r0=r2MVNr0,r2;r0=not r2,MVN stands for move negated:,r2:0101

7、 0011 1010 1111 1101 1010 0110 1011r0:1010 1100 0101 0000 0010 0101 1001 0100,Data processing instructions(contd)ARMs register comparison operations:,CMP r1,r2;set cc on r1 r2CMNr1,r2;set cc on r1+r2TSTr1,r2;set cc on r1 and r2TEQr1,r2;set cc on r1 xor r2,results of subtract,add,and,xor are NOT stor

8、ed in any registersThe condition code bits(cc)in the CPSR are set or cleared by these instructions Ex CMN r1,r2:N=1 if MSB of the addition(r1+r2)results in 1 else N=0Z=1 if the result of the addition is zero,else Z=0C is set to the carry-out of the additionV is set to the overflow of the addition,Da

9、ta processing instructions(contd)ARM has clever feature.In any data processing instructions,we can apply to the second register a shift operation For example:,ADD r3,r2,r2,LSL#3,Here LSL means logical shift left by the specified number of bits.Note that this is still a single ARM instruction,execute

10、d in a single cycle In most processors,this is a separate instruction,while ARM integrates this shifting into the ALU It is also possible to use a register value to specify the number of bits the second operand should be shifted by:,ADD r3,r2,r2,LSL r2,Data processing instructions(contd)Six possible

11、 ARM shift operations can be used,00000,00000,31,0,0,31,LSL#5,LSR#5,LSL:fill the vacated bits at the least significant end of the word with zeros.LSR:fill the vacated bits at the most significant end of the word with zeros.,Data processing instructions(contd)ASL:this is the same as LSK.ASR:fill the

12、vacated bits at the most significant end of the word with zeros if the source operand was positive,and with ones it is negative.,0,1,11111 1,00000 0,31,0,0,31,ASR#5,positive operand,ASR#5,negative operand,Data processing instructions(contd)ROR:the bits which fall off the least significant end are us

13、ed to fill the vacated bits at the most significant end of the word.RRX:rotate right extended by 1 place:the vacated bit(bit 31)is filled with the old value of the C flag and the operand is shifted one place to the right.This is effectively a 33 bit rotating using the register and the C flag,31,0,0,

14、31,ROR#5,RRX,C,C,Data processing instructions(contd)ARM has a number of multiply instructions:-produce the product of two 32-bit binary numbers held in the registers.-result of 32-bit by 32-bit is 64 bits,.The entire 64-bit result is stored in two registers.Sometimes only 32 bits of the product are

15、saved-Multiply Accumulate instruction also adds the product to a running total.,MUL r4,r3,r2;r4=r3*r2 MLA r4,r3,r2,r1;r4=(r3*r2)+1,Difference from the other arithmetic operations:-immediate second operands are not supported-the result register cannot be the same as the second source register.,ARM DA

16、TA transfer instructions 3 basic forms of data transfer instructions:-single register load/store instructions.-Multiple register load/sore instructions-single register swap instruction(combined lad and sore)Use a value in one register(called the base register)as a memory address and either loads the

17、 data value from that address into a designation register or stores the register value to memory:LDRr0,r1;r0=mem32r1STR r0,r1;mem32r1=r0 This is called register-indirect addressing,ARM DATA transfer instructions(contd)to load or store from or to a memory locations,an ARM register must be initialized

18、 to contain the address of that location.In order to do that a pseudo instruction is used:ADR(the assembler translate it to a real data processing instruction)Ex.Copy of data within memory TABLE1 to TABLE2,CopyADRr1,TABLE1ADR r2,TABLE2LDRr0,r1STRr0,r2.TABLE1.TABLE2.,ARM DATA transfer instructions(co

19、ntd)Extend the copy program further to copy the next word:,CopyADRr1,TABLE1ADR r2,TABLE2LDRr0,r1STRr0,r2ADD r1,r1,#4ADD r2,r2,#4.TABLE1.TABLE2.,Simplify with pre-indexed addressing mode:LDR r0,r1,#4;r0=mem32 r1+4,Base address,offset,Effective address,ARM DATA transfer instructions(contd)pre-indexed

20、addressing does not change r1.Sometimes,it is useful to modify the base register to point to the new address.This is achieved by adding a!,and we then have auto-indexing:LDR r0,r1,#4!;r0=mem31 r1+4;r1=r1+4The!indicates that the instruction should update the base register after the data transfer.In p

21、ost-indexed addressing,the base address is used without an offset as the transfer address,after which it is always modified.Using this,we can improce the program mpre LDR r0,r1,#4;r0=mem32r1;r1=r1+4,CopyADRr1,TABLE1ADR r2,TABLE2LDRr0,r1,#4STRr0,r2,#4.TABLE1.TABLE2.,ARM DATA transfer instructions(con

22、td),LDR and STR instructions are repeated until the required number of values has been copied into TABLE2,and then the loop is exited,ARM DATA transfer instructions(contd),The size of the data item which is transferred may be a single 8-bit byte instead of a 32-bit word.This option is selected by ad

23、ding a letter B onto the symbolic operation code:,LDRB ro,r1;r0=mem8 r1,LDR and STR instructions only load/store a single 32-bit word,ARM DATA transfer instructions(contd)Multiple register data transfersARM can load/store any subset of its register in a single instruction by using load/store multipl

24、e instructions.For example:,LDMIA r1,r0,r2,r4;r0=mem32r1;r2=mem32r1+4;r4=mem32r1+8,Base_addr,r0,r1,r2,r3,r4,Base_addr,Base_addr+8,Base_addr+4,Memory,STMIAr1,r0,r2,r4,Base register r1 has not been changed,ARM DATA transfer instructions(contd)We can update the vase register by adding!after it:,LDMIA r

25、1!,r2-r9;r2=mem32r1;.;r9=mem32r1+28;r1=r1+32,Load multiple,Incrementbase address,Update r1 After use,Base address is incremented after it is used,Load registers r2 to r9,ARM DATA transfer instructions(contd)Example of moving 8 bytes from a source memory location to a destination memory location,ADR

26、r0,src_addr;initialize src_addrADR r1,deat_addr;initialize dest_addrLDMIA r0!,r2 r9;fetch 8 words from memory;and update r0=r0+32STMIA r1,r2 r9;copy 8 words to mem,r1 unchanged,When using LDMIA and STMIA instructions we;1.increment the address in memory to load/store our data2.The increment of the a

27、ddress occurs AFTER the address is used.Four different forms of load/store instructions are available:increment AfterLDMIA and STMIAincrement BeforeLDMIB and STMIBdecrement AfterLDMDA and STMDAdecrement Before LDMDB and STMDB,ARM DATA transfer instructions(contd)Multiple register transfer addressing

28、 modes,r9,r9,r9,r9,STMIA r9!,r0,r1,r5,STMIB r9!,r0,r1,r5,&1000,&100c,&1018,&1018,&100c,&1000,ARM DATA transfer instructions(contd)Multiple register transfer addressing modes,r9,r9,r9,r9,STMDA r9!,r0,r1,r5,STMDB r9!,r0,r1,r5,&1000,&100c,&1018,&1018,&100c,&1000,ARM DATA transfer instructions(contd)Sta

29、ck addressing A stack is last-in-first-out which supports dynamic memory allocation,that is,memory allocation where the address to store a data value is not known at the time the program is compiled.A stack is usually implemented as a linear structure which grows up(an ascending stack)or down(a desc

30、ending stack)memory as data is added to it and shrinks back as the data is removed.A stack pointer holds the current top of the stack,either by1.pointing to the last valid data item pushed onto the stack(a full stack)or2.by pointing to vacant slot where the next data item will be placed(an empty sta

31、ck)ARM multiple register transfer instructions supports all four forms of stack,ARM DATA transfer instructions(contd)Stack addressing Full ascending:the stack grows up through increasing memory addresses and base register points to the highest address containing a valid item,r9,r9,STMFA r9!,r0,r1,r5

32、,&1018,&100c,&1000,ARM DATA transfer instructions(contd)Stack addressingEmpty ascending:the stack grows up through increasing memory addresses and base register points to the first empty location above the stack,r9,r9,STMEA r9!,r0,r1,r5,&1000,&100c,&1018,ARM DATA transfer instructions(contd)Stack ad

33、dressing Full descending:the stack grows down through decreasing memory addresses and base register points to the lowest address containing a valid item,r9,r9,STMFD r9!,r0,r1,r5,&1018,&100c,&1000,ARM DATA transfer instructions(contd)Stack addressingEmpty descending:the stack grows down through decre

34、asing memory addresses and base register points to the first empty location below the stack,r9,r9,STMED r9!,r0,r1,r5,&1000,&100c,&1018,ARM DATA transfer instructions(contd)Swap InstructionThe swap instruction is a special case of load instructionIt swaps the content of memory with the contents of a

35、registerExample,preMem320 x8000=0 x12345678r0=0 x00000000,r1=0 x11112222,r2=0 x00008000 Swpr0,r1,r2postMem320 x8000=0 x11112222r0=0 x12345678,r1=0 x11112222,r2=0 x00008000,Control flow Instructions(contd)The basic branch instruction is:,BLabel;unconditionally branch to Label.Label.,Conditionally bra

36、nched instructions can be used to control loops:,MOV r0,#10;initialize loop counter r0Loop.SUB r0,r0,#1;decrement loop counterCMP r0,#0;is it zero?BNE loop;repeat,Control flow Instructions(contd)ARM Branch instructions,Control flow Instructions(contd)Conditional execution Conditional execution allie

37、s not only to branches,but to all ARM instructions For Example,CMP r0,#5;if(r0!=5 thenBEQ BYPASSADD r1,r1,r0SUB r1,r2,r2BYPASS.,Can be replaced by a smaller and faster sequence:,CMP r0,#5;if(r0!=5 thenADDNE r1,r1,r0SUBNE r1,r2,r2BYPASS.,Here the ADDNE and SUBNE instruction are executed only if Z=0 i

38、.e.CMP instruction gives non-zero result,Control flow Instructions(contd)Branch and Link instructions A common requirement in a program is to be able to branch to a subroutine and resume the original code sequence when the subroutine has completed.ARM offers this functionality through branch and lin

39、k instruction which apart from branching to the subroutine,also saves the address of the instruction following the branch in the link register,r14.Example:,BL SUBR;branch to SUBR;return to hereSUBR.;subroutine entry pointMOV pc,r14;return,Control flow Instructions(contd)Branch and Link instructions

40、A subroutine that calls another subroutine should first save r14 before calling the subroutine,otherwise the new return address will override the old one and it will not be possible to find the way back to the original caller The normal mechanism used can be to push r14 onto a stack and restore it b

41、ack when required.,BL SUB1SUB1STMFD r13!,ro-r2,r14;save work and link registerBL SUB2LDMFDr13!,r0-r2,r14;restore work regs and returnSUB2.MOVpc,r14;copy r14 into r15 to return,Control flow Instructions(contd)Supervisor calls SWI software interrupt instruction Forces execution to jump to the vector a

42、ddress 0 x00000008,from where then further jumps to ISRThe supervisor provides trusted way to access system resources which appear to the user-level program rather like special subroutine accesses.SWI instruction can be used to call these functions.,Thumb instruction setFeatures of Thumb state All T

43、humb instructions are 16 bits in length Thumb has higher code density the space taken by an executable program-than ARM.On average a Thumb implementation of the same code takes up around 30%less memory than equivalent ARM implementation.Most code written for Thumb is in high-level language such as C

44、 and C+.Each Thumb instruction is related to a 32-bit ARM instruction.,Decoder,ADD ro,#3,ADDS ro,ro,#3,Thumb 16-bit instruction,ARM 32-bit instruction,Thumb instruction decoding,Thumb instruction setFeatures of Thumb state(contd)In Thumb only the low registers r0 to r7 are fully accessible.The highe

45、r registers r8 to r12 are only accessible with MOV,ADD,or CMP instructions.In thumb only the branch instructions are conditionally executed.The barrel shifter operations are separate instructions The Thumb mode includes POP and PUSH instructions as stack operations.These instructions only support a

46、full descending stack.There are no Thumb instructions to access the coprocessors,cpsr and spsr.If any interrupt or exception flag is raised in Thumb state,the processor automatically reverts back to ARM state to handle the exception ARM-Thumb interworking is the name given to the method of linking ARM and the Thumb code together for both assembly and C/C+.It handles the transition between the two states.,