Synplicity培训以及试验相关资料.ppt
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1、,Performance,Advanced Synthesis with theSynplify Pro ToolWinter/Spring 2003Course Outline,IntroductionHDL Coding for Lab 1Technology IndependentAttributesTechnology SpecificAttributes,Advanced SynthesisTopics for Xilinx FPGALab 3MultiPoint Synthesis Flow,Lab 4Advanced SynthesisTopics for Altera CPLD
2、Complex Clocking,Retiming,Lab 2,Lab 5,2,FPGAsolutions,3,s,4,Introduction Introduction,HDL,Coding for Performance,IntroductionSynplicity Solutions,Synplify ASIC,Certify,Introduction,ASIC solutionsSynplicitybrings leading-edgelogic synthesis andverification productsto FPGA and ASICdesigners,Synplify P
3、roand SynplifyAmplifyPhysical Optimizer,5,TM,6,FPGA Product Line OverviewAmplify Physical OptimizerPhysical Synthesis for FPGAs Highest Circuit Performance Fastest Timing Closure Option to Synplify ProSynplify Pro Tool Challenging Designs Complex Projects The Ultimate in FPGASynthesisSynplify Tool F
4、ast Easy to Use Excellent ResultsIntroductionFPGA Synthesis with the Synplify Pro ToolMarket Leader in FPGA Synthesis,Ultra,Fast,uB.E.S.T.,algorithms,Easy,to Use,uLanguage,sensitive,Text EditoruHDL Analyst tooluS.C.O.P.E.,Excellent,Results,uTiming-driven,uDirect,mapping to,technology-specificprimiti
5、vesIntroduction,7,8,Getting HelpOnline Help,u Select,Help-Help,or F1 function key from the Synplify Pro UI,Synplify Pro User Guide,u Pdf,file found in/docs,Synplify Pro Reference Guide,u Pdf,file found in/docs,Synplicity Supportu Synplify Online SupportSOS and Synplify Newsgroup http:/news:/Synplify
6、 First Level Support Can be accessed from S.O.Su Send email to,u Call,the Technical Support Hotline at(408)215-6000,IntroductionHDL Coding for Performance Introduction,HDLHDL Coding Techniques for Performance,Coding for Performance,9,10,Overview,Discuss,various HDL coding issues that affect,performa
7、nce,uShared,Expressions,uShannon,Expansion,uOperand ReorderinguPriority EncodingParallel Case,uRAM,Inferencing,uOther coding issuesLatch GenerationSensitivity ListHDL Coding Techniques for PerformanceCommon Boolean ExpressionsDefinition,u Share,identical boolean(sub-)expressions(&,|,),Pros and Cons,
8、u Saves,Area,u Done,automatically,u Generally have minimal timing impactu Some situations require source code changesmanual replicationWhen to use it,u Share,common expressions to save area(automatic),u Manually replicate expressions to control Large number of loads within a black box Reduce loading
9、 on a critical pathHDL Coding Techniques for Performance,loading,11,12,Common Boolean Expressions Example,uDesign,details,Goal:meet load restriction of 10 Design has two black boxes,each with 8 loads on the en input The Synplify Pro tool does not know about loading within theblack boxes,Original,Des
10、ign,ua_en,and b_en were shared,resulting in 16 loads on en,Fixed,Design,uManually,forced the a_en and b_en to remain separate,uEach enable signal drive only one black box(8 loads)HDL Coding Techniques for PerformanceCommon Boolean Expressionsmodule function_a(in1,in2,en,out),/*synthesis syn_black_bo
11、x*/;input en;input 7:0 in1,in2;output 7:0 out;endmodulemodule function_b(in1,in2,en,out)/*synthesis syn_black_box*/;input en;input 7:0 in1,in2;output 7:0 out;endmodule,module bb_load(a1,a2,b1,b2,opcode,clk,rst,a_out,b_out);input clk,rst;input 3:0 opcode;input 7:0 a1,a2,b1,b2;output 7:0 a_out,b_out;r
12、eg 7:0 a1_reg,a2_reg,b1_reg,b2_reg;wire 3:0 a_opcode;wire 3:0 b_opcode;wire a_en;wire b_en;always(posedge clk or negedge rst),if(!rst)begina1_reg=8h00;a2_reg=8h00;b1_reg=8h00;b2_reg=8h00;endelse begina1_reg=a1;a2_reg=a2;b1_reg=b1;b2_reg=b2;endassign a_opcode=opcode;assign b_opcode=opcode;assign a_en
13、=(a_opcode=4b1011)?1b1:1b0;assign b_en=(b_opcode=4b1011)?1b1:1b0;function_a bb_A(a1_reg,a2_reg,a_en,a_out);function_b bb_B(b1_reg,b2_reg,b_en,b_out);endmodulea_en being shared between function_a and,HDL Coding Techniques for Performance,function_b,causing load on it to be(8+8)=16,13,b,b,14,Common Bo
14、olean Expressions,Applying syn_keep onthe signals a_opcode andb_opcode,divide the loadon the enable signal tomeet the designrequirement.,module function_a(in1,in2,en,out)/*synthesis syn_black_box*/;input en;input 7:0 in1,in2;output 7:0 out;endmodulemodule function_b(in1,in2,en,out)/*synthesis syn_bl
15、ack_box*/;input en;input 7:0 in1,in2;output 7:0 out;endmodule,module bb_load(a1,a2,b1,b2,opcode,clk,rst,a_out,b_out);input clk,rst;input 3:0 opcode;input 7:0 a1,a2,b1,b2;output 7:0 a_out,b_out;reg 7:0 a1_reg,a2_reg,b1_reg,b2_reg;wire 3:0 a_opcode/*synthesis syn_keep=1*/;wire 3:0 b_opcode/*synthesis
16、syn_keep=1*/;wire a_en;wire b_en;always(posedge clk or negedge rst),if(!rst)begina1_reg=8h00;a2_reg=8h00;b1_reg=8h00;b2_reg=8h00;endelse begina1_reg=a1;a2_reg=a2;b1_reg=b1;b2_reg=b2;endassign a_opcode=opcode;assign b_opcode=opcode;assign a_en=(a_opcode=4b1011)?1b1:1b0;assign b_en=(b_opcode=4b1011)?1
17、b1:1b0;function_a bb_A(a1_reg,a2_reg,a_en,a_out);function_b bb_B(b1_reg,b2_reg,b_en,b_out);endmoduleHDL Coding Techniques for PerformanceShannon Expansion Definition,uBoolean,Transformation,F(a,b,c)=aF(0,b,c)+aF(1,b,c),uExample,-F=a+ac(2 to 1 Mux),F(a,b,c)=aF(0,b,c)+aF(1,b,c)a(1b+0c)+a(0b+1c)a+ac,Pr
18、os,and Cons,uCan,dramatically improve timing on critical signals,uMay require substantial changes in the codeuIncreases areaHDL Coding Techniques for Performance,uA,15,16,Shannon Expansion,WhenuPath,to use itis far from meeting timing(25%or more off),If path is within 20%of the goal,try Synthesis an
19、d P&Rconstraints first.,uCritical,path has many logic levels,The Synplify Pro tool may need to break complex paths limitingits ability to prioritize critical signals.small subset of signals have priorityIf all signals feeding a cone of logic are equally critical there isno advantage to prioritize on
20、e over the other.,uNeed,to move critical signals past an operator,The Synplify Pro tool cannot replicate operators(+,-,*,.)HDL Coding Techniques for PerformanceShannon Expansion Example,Design,details,u65,MHz goal,uSignal late has input delay of 8nsutarget technology:Actel 54SX Std,Original,design,u
21、Speed,67.6MHz,Area:35 Cells,Fast,design(prioritize late as much as,possible-Shannon expansion),uSpeed,77.2MHz,Area:42 Cells,HDL Coding Techniques for Performance,17,18,Shannon Expansion Example,Requested Estimated Requested Estimated,module shannon(in0,in1,in2,late,en,out);,Clock,Frequency Frequency
22、 Period,Period Slack,input 7:0 in0,in1,in2;,-System 70.0 MHz 67.6 MHz 14.286 14.785-0.500=,inputoutput,late,en;out;,assign out=(8late|in0)+in1)=in2)endmoduleOriginal source-late traverses an ORgate,an adder,a comparator,and anAND gateHDL Coding Techniques for PerformanceShannon Expansion Example(Con
23、td),Requested Estimated Requested EstimatedClock Frequency Frequency Period Period Slack-System 70.0 MHz 77.2 MHz 14.286 12.949 1.337=,module shannon_fast(in0,in1,in2,late,en,out);input 7:0 in0,in1,in2;input late,en;output out;,wire late_eq_0,late_eq_1;assign late_eq_0=(81b0|in0)+in1)=in2)endmoduleR
24、e-coding using Shannon Expansionreduces the number of levels of logic fromlate to out.HDL Coding Techniques for Performance,A A,uA,19,“,“,20,Operand Reordering Definition,uUse,algebraic identities to prioritize signals,“+B=C”is equivalent to“=C-B”,Pros,and Cons,uCan,dramatically improve timing on cr
25、itical signals,uUsually no area penaltyuRequires minor changes to source code,When,to use it,small subset of signals have priorityuNeed to move critical signals past an operatorHDL Coding Techniques for PerformanceOperand Reordering Example,uDesign,Details,54 MHz goalSignal ADDR has an input delay o
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