FM TransmitterDepartment of Electrical and … .ppt

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1、FM Transmitter,FM Modulation using VCO,Vin,fout,-Gain of VCO,-Free Running Frequency of VCO,Corresponding DC bias,1,Block Diagram,DC BiasVcc/2,VCO,PA,Input,Chipset,4046 Phase-Locked Loop LM7171 Wide-Band Power Amplifier 741 Op Amp,4046 PLL,Only use the VCO,4046 VCO Characteristic,C1=100pF,Schematic,

2、PCB Layout Considerations,The signal traces should be short and wide to lower the impedance.The width of the signal traces has to satisfy current driving capacity.Any used board area should be shorted to ground to reduce AC noise.Sockets and pads will induce extra capacitance,so components should be

3、 directly soldered to board.Surface mount components are preferred over discrete ones for less lead inductance.,PCB Layout,Measured Results,Carrier Frequency:15MHz Bandwidth:Controllable Output Power:500mW,FM Receiver,FM Demodulation using PLL,PFD,LF,VCO,Ve,in,2,Loop Filter Design,3,VCO Design,VCO f

4、ree running frequency=Carrier Frequency VCO Frequency Range is no smaller than Bandwidth Large VCO gain will increase PLL natural frequency n and thus improves PLL tracking capability,Block Diagram,LNA,PFD,LF,VCO,Amp,BPF,Chipset,4046 PLL CLC425 Wide-band LNA,4046 PLL,Schematic,PCB Layout,Superhetero

5、dyne FM Receiver,Block Diagram,Amp,InputMatching,Mixer,IF Amp+IF Filter,LO,FMDemodulator,Chipset,TDA7000 FM Radio LM3875 Audio Power Amplifier,TDA7000,4,IF Filter,Quadrature Demodulator,fin,Vout,IF Harmonic Distortion,IF=70kHz,IF Distortion Suppression,FLL,Correlator,To suppress interstation noise,N

6、ot Modulated Lightly Modulated Heavily Modulated,Schematic,PCB Layout,Monolithic FSK Transmitter,5,Block Diagram,Inverter,NAND 2 Input,NAND 3 Input,NAND 4 Input,NOR 2 Input,XOR,Transmission Gate,Edge-Triggered D Flip-Flop,D Flip-Flop with CLEAR,Voltage Comparator,8-to-3 Encoder,A/D Converter,Paralle

7、l-Serial Shift Register,Phase-Frequency Detector,VCO,Dual Modulus Prescaler,6,Output Driver,To drive capacitive load with minimum delay,Capacitor Driving Capability,CL=100p,f=50MHz,Synthesizer,Synthesizer Response,ADC and SR Response,Chip Layout,Digital Switching Noise,7,Noise Mechanism,Digital swit

8、ching injects current into substrate through various kinds of capacitance,which propagates through the substrate and affects analog circuits.Digital switching draws current from power supply rail with impedance and thus creates voltage drop on power supply rail.,Digital Switching Noise in PLL,PLL is

9、 a typical mixed-signal integrated circuit,PFD,LF,VCO,/N,Noise Coupling,Simulation Results,Error Voltage,VCO output,Noise Reducing Techniques,Use Differential Topology Separate Power Supply Rails Use guard rings Multi-chip Module Heterogeneous integration,Test Structure 1,PFD,LF,VCO,/N,All building

10、blocks share power supply rails,Chip Layout 1,Test Structure 2,PFD,LF,VCO,/N,The counter uses separate power supply rails,Chip Layout 2,Test Structure 3,PFD,LF,VCO,/N,The counter uses separate power supply rails The PFD and VCO are shielded and ring guarded,Guard Ring,p+,p+,P-type Substrate,Sink the

11、 coupling,On-Chip Shielding,Metal 3,ICs,Via2,Via1,Contact,Ohmic Contact,Radiation,Chip Layout 3,Test Structure 4,PFD,LF,VCO,/N,The counter uses separate power supply rails Use guard rings around PFD and VCO Implement LC VCO,LC VCO,Lower Phase Noise than Ring Oscillator,Oscillator Basics,-Tank Loss,P

12、ositive feedback of 2n phase shift Unity loop gain,Phase noise is reverse proportional to Q,8,Chip Layout,Electromagnetic Coupling,Microstrip Line Coupling,L,S,W,1,2,3,4,9,Electric Field Distribution,Even Mode,Odd Mode,Impedance Matrix,-propagation constant,Zoe-even mode characteristic impedanceZoo-

13、odd mode characteristic impedance,Different Configurations,Low Pass,Band Pass,Band Pass,Band Pass,Experiment Setup,Results,The coupling depends on L,W,S,and,Integrated Inductor Coupling,Coupling between integrated spiral inductors Coupling from spiral inductors to transistors,10,2.5D Integrated Indu

14、ctor,11,Interference Effects on PLL Performance,12,References,Jerry D.Gibson,Principles of Digital and Analog CommunicationsFloyd M.Gardner,Phaselock TechniquesRoland E.Best,Phase-Locked Loops Theory,Design,and ApplicationsW.H.A.Van Dooremolen and M.Hufschmidt,A complete FM radio on a chipR.Jacob Ba

15、ker,Harry W.Li,David E.Boyce,CMOS Circuit Design,Layout,and SimulationJ.Navarro Soares and W.A.M.Van Noije,A 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique,IEEE Journal of SSCC,Vol.34,No.1,Jan 1999Patrik Larsson,Measurements and Analysis of PLL Jitte

16、r Caused by Digital Switching Noise,IEEE Journal of SSCC,Vol.36,No.7,July 2001Dan H.Wolaver,Phase-Locked Loop Circuit DesignE.M.T.Jones and J.T.Bolljahn,Coupled-Strip-Transmission-Line Filters and Directional Couplers,IRE Trans on Microwave Theory and Techniques,1956A.O.Adan,M.Fukumi,K.Higashi,T.Suy

17、ama,M.Miyamoto,M.Hayashi,Electromagnetic Coupling Effects in RFCOMS Circuits,2002 IEEE MTT-S Digest Jaime Aguilera and Joaquin De No,A Guide for On-Chip Inductor Design in a Conventional CMOS Process for RF Application Murat F.Karsi,William C.Lindsey,Effects of CW Interference on Phase-Locked Loop Performance,IEEE Trans on Comm,Vol.48,No.5,May 2000,