数字时钟外文翻译.doc

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1、 外文资料翻译L ED using digital tube digital display its high-brightness, indicating the advantages of intuitive intelligence is widely used in areas such as equipment and household appliances. AT89C52This article describes a single-chip microcomputer as the core, to a total of anode high-brightness LED L

2、 ED as a display composed of seven figures show that the practical design of multi-function electronic clocks, the clock shows a week, hour, minute, second, it can be switched to year, month, day showed that the whole point of music at the same time and from time to time the alarm time and other fun

3、ctions can also be used for electronic stopwatch.Clock circuit is the heart of the computer, which controls the rhythm of the work of the computer is through the completion of complex sequential circuits function in different directions.Clock, since it was invented that day on, peoples lives has bec

4、ome an indispensable tool, especially in this era of efficient, the clock is in the human production and living, learning and other fields is widely. However, with the passage of time, people not only to the requirements of the clock is getting higher and higher precision, and functional requirement

5、s for the clock more and more, the clock has not only a tool used to display time, in many practical applications It also needs to be able to achieve more other functions. Features such as alarm clock, calendar display, temperature measurement function, humidity measurements, voltage measurements, f

6、requency measurements, have been under-voltage alarm function. Digital clocks to the peoples production and life has brought great convenience, but also greatly expands the time feature the original clocks. Such as regular auto-alarm, Automatic time-ling, time process automation, from time to time b

7、roadcast, from closed-circuit automatic lights, oven timer switch, on-off power equipment, electrical and even a variety of timing is automatically enabled, all of which are based on digital clocks and watches based. It can be said that the design of the significance of multi-function Digital Clock

8、Digital Clock is not just itself, a greater significance of the multi-function digital clock in a number of real-time control systems. In many practical applications, as long as the digital clock circuit of the programs and hardware to a certain degree of modification could be useful for real-time c

9、ontrol system, which applied to the actual work and production to. Thus, digital clock and to expand its applications, has a very practical significance. With the development of human civilization, science and technology, there is the request of the clock continues to improve. Clock has not only see

10、n as a tool to display the time, in many practical applications also need to be able to achieve more other functions. High-precision, multifunction, small size, low power consumption, is the development trend of the modern clock. In this trend, digital clock, multifunction clock has become the moder

11、n design of the production of research-led direction. This article is based on this design direction for the control of a single-chip core design requirements of a multi-function indicators in line with the digital clock. The design is based on the principle of single-chip technology to chip AT89C52

12、single-chip microcomputer as the core controller, through the production of hardware and software procedures for the preparation, design to produce a multi-functional digital clock system. The clock system mainly by clock module, alarm module, the ambient temperature detection module, liquid crystal

13、 display module, control module and the keyboard signal prompted module. System is simple and clear user interface that can 4V 7V DC power under normal operation. Able to accurately display time (display format hh: mm: seconds seconds, 24-hour system), may be time to adjust at any time, with clock t

14、ime settings, alarm on / off, only to make functions, where the clock to measure the ambient temperature and displayed. Hardware and software design into the guiding ideology, give full play to the single-chip features, most of the functions through software programming to achieve, the circuit is si

15、mple and clear, high system stability. At the same time, the clock system also has the power of small, low cost, and highly practical. System components as a result of less use, single-chip occupied by the I / O port not more than, the system has a certain degree of scalability.Clock design is no th

16、eory of discrete logic, programmable logic, or using full-custom silicon devices of any digital design, in order to successfully operate and reliable clock is crucial. Poor design of the clock in the limits of temperature, voltage deviation or the manufacturing process will result in the case wrong,

17、 and debugging difficult, spending a lot. In the design of FPGA / CPLD clock when several types of commonly used. Clock can be divided into the following four types: global clock, clock gating, multi-level logic clock clock and volatility. Multi-clock system to include the above-mentioned four types

18、 of any combination of the clock. No matter what methods are the real circuit clock tree can not achieve the ideal assumption that the clock, so we must be based on an ideal clock, the clock real work to build a model to analyze the circuit, so as to make the circuit performance and the practical wo

19、rk as expected . Clock in the actual model, we have to consider the spread of clock-tree skew, vertical jump and absolute bias and other uncertainties. To register, the clock was working along the arrival of the data terminal when it should have been stable, so as to ensure that the work along the s

20、ampling clock to the accuracy of the data, this data preparation time that we call set-up time (setup time). Data should also be working along the clock to maintain over a period of time, this period of time known as the hold time (hold time). Global clock for a design project, the global clock (or

21、clock synchronous) is the simplest and most predictable clock. In the PLD / FPGA design of the clock the best options are: by a dedicated global clock input pins of a single master clock-driven clock design projects to each flip-flop. As long as possible should be used in the design of global clock

22、projects. PLD / FPGA has a dedicated global clock pins, the device is directly connected to each register. Global clock to provide such a device in the shortest possible delay to the output clock. Clock-gated in many applications, the entire design of the overall use of external clock is not possibl

23、e or practical. With the product of PLD logic array clock (that is, the clock is generated by the logic), to allow arbitrary function alone all trigger clock. However, when you use the array clock, the clock should be carefully analyzed the function, in order to avoid glitches. Usually constitute th

24、e array clock clock-gated. Clock gating often interface with the microprocessor, and used the address to write to control the pulse line. However, when using combination of flip-flop when the clock function, usually there is a clock-gated. If the following conditions, such as clock gating can be as

25、reliable as global clock work: Drive the clock logic must contain only one and the door or a or gate. If any additional work in some state of logic, the competition will be the burr. A logic gate input as the actual clock, and the logic gate must be of all other input as the address or control lines

26、, in relation to their compliance with the establishment and maintenance of clock time bound. Multi-level logic generated clock when the clock-gating logic of the combination of more than one (or more than the individual and doors or or gate), the evidence of the reliability of the design of the pro

27、ject has become very difficult. Even if the prototype or simulation results show that there is no static dangerous, but in fact the risk may still exist. In general, we should not use multi-level combinational logic to clock the flip-flop in the PLD design. Traveling-wave clock clock another popular

28、 use of traveling-wave circuit is the clock, that is, the output of a flip-flop used as a clock input of another flip-flop. If careful design, traveling-wave clock can be the same as the global clock to work reliably. However, the traveling-wave clock made from time to time with the calculation of t

29、he circuit becomes very complicated. Line-wave traveling-wave clock flip-flop of the chain have a greater clock time between the offset and exceed the worst case the set-up time, hold time and clock to the output circuit of the delay, allowing the system to the actual slowed down. Multi-clock system

30、, many system requirements within the same multi-PLD clock. The most common example is the two asynchronous interfaces between microprocessors, or microprocessors and asynchronous communication channel interface. As the clock signal between the two requirements to establish and maintain a certain ti

31、me, so that the above application from time to time the introduction of additional constraints. They also requested that some asynchronous synchronization signal. In many applications, only the synchronization of asynchronous signals is not enough, when the system of two or more non-homologous clock

32、, the data it is difficult to establish and maintain the time to be assured that we will face the complex matter of time . The best way is to all non-homologous clock synchronization. PLD internal use of the lock loop (PLL or DLL) is a very good, but not all of PLD with a PLL, DLL, and chip PLL with

33、 most expensive, so unless there are special requirements, the general occasions PLL can not use with the PLD.At this time we need to take to enable the use of the D flip-flop-side, and the introduction of a high-frequency clock. 采用L ED 数码管的数字显示以其亮度高、显示直观等优点被广泛应用于智能仪器及家用电器等领域. 本文介绍一种以AT89C52单片机为核心,以

34、共阳极高亮度L ED 数码管作为显示器件组成7 位数字显示的实用多功能电子时钟的设计,该时钟可显示星期、时、分、秒,也可切换为年、月、日显示,同时具有整点音乐报时及定时闹钟等功能,也可作电子秒表使用。时钟电路是计算机的心脏, 它控制着计算机的工作节奏就是通过复杂的时序电路完成不同的指令功能的。时钟，自从它被发明的那天起，就成为人们生活中必不可少的一种工具，尤其是在现在这个讲究效率的年代，时钟更是在人类生产、生活、学习等多个领域得到广泛的应用。然而随着时间的推移，人们不仅对于时钟精度的要求越来越高，而且对于时钟功能的要求也越来越多，时钟已不仅仅是一种用来显示时间的工具，在很多实际应用中它还需要能

35、够实现更多其它的功能。诸如闹钟功能、日历显示功能、温度测量功能、湿度测量功能、电压测量功能、频率测量功能、过欠压报警功能等。钟表的数字化给人们的生产生活带来了极大的方便，而且大大地扩展了钟表原先的报时功能。诸如定时自动报警、按时自动打铃、时间程序自动控制、定时广播、自动起闭路灯、定时开关烘箱、通断动力设备、甚至各种定时电气的自动启用等，所有这些，都是以钟表数字化为基础的。可以说，设计多功能数字时钟的意义已不只在于数字时钟本身，更大的意义在于多功能数字时钟在许多实时控制系统中的应用。在很多实际应用中，只要对数字时钟的程序和硬件电路加以一定的修改，便可以得到实时控制的实用系统，从而应用到实际工作与

36、生产中去。因此，研究数字时钟及扩大其应用，有着非常现实的意义。随着人类科技文明的发展，人们对于时钟的要求在不断地提高。时钟已不仅仅被看成一种用来显示时间的工具，在很多实际应用中它还需要能够实现更多其它的功能。高精度、多功能、小体积、低功耗，是现代时钟发展的趋势。在这种趋势下，时钟的数字化、多功能化已经成为现代时钟生产研究的主导设计方向。本文正是基于这种设计方向，以单片机为控制核心，设计制作一个符合指标要求的多功能数字时钟。本设计基于单片机技术原理，以单片机芯片AT89C52作为核心控制器，通过硬件电路的制作以及软件程序的编制，设计制作出一个多功能数字时钟系统。该时钟系统主要由时钟模块、闹钟模块

37、、环境温度检测模块、液晶显示模块、键盘控制模块以及信号提示模块组成。系统具有简单清晰的操作界面，能在4V7V直流电源下正常工作。能够准确显示时间（显示格式为时时：分分：秒秒，24小时制），可随时进行时间调整，具有闹钟时间设置、闹钟开/关、止闹功能，能够对时钟所在的环境温度进行测量并显示。设计以硬件软件化为指导思想，充分发挥单片机功能，大部分功能通过软件编程来实现，电路简单明了，系统稳定性高。同时，该时钟系统还具有功耗小、成本低的特点，具有很强的实用性。由于系统所用元器件较少，单片机所被占用的I/O口不多，因此系统具有一定的可扩展性。时钟设计无沦是用离散逻辑、可编程逻辑，还是用全定制硅器件实现的

38、任何数字设计，为了成功地操作，可靠的时钟是非常关键的。设计不良的时钟在极限的温度、电压或制造工艺的偏差情况下将导致错误的行为，并且调试困难、花销很大。在设计FPGA/CPLD时通常采用几种时钟类型。时钟可分为如下四种类型：全局时钟、门控时钟、多级逻辑时钟和波动式时钟。多时钟系统能够包括上述四种时钟类型的任意组合。无论采用何种方式，电路中真实的时钟树也无法达到假定的理想时钟，因此我们必须依据理想时钟，建立一个实际工作时钟模型来分析电路，这样才可以使得电路的实际工作效果和预期的一样。在实际的时钟模型中，我们要考虑时钟树传播中的偏斜、跳变和绝对垂直的偏差以及其它一些不确定因素。对于寄存器而言，当时钟

39、工作沿到来时它的数据端应该已经稳定，这样才能保证时钟工作沿采样到数据的正确性，这段数据的预备时间我们称之为建立时间（setup time）。数据同样应该在时钟工作沿过去后保持一段时间，这段时间称为保持时间（hold time）。全局时钟对于一个设计项目来说，全局时钟(或同步时钟)是最简单和最可预测的时钟。在PLD/FPGA设计中最好的时钟方案是：由专用的全局时钟输入引脚驱动的单个主时钟去钟控设计项目中的每一个触发器。只要可能就应尽量在设计项目中采用全局时钟。PLD/FPGA都具有专门的全局时钟引脚，它直接连到器件中的每一个寄存器。这种全局时钟提供器件中最短的时钟到输出的延时。门控时钟在许多应用

40、中，整个设计项目都采用外部的全局时钟是不可能或不实际的。PLD具有乘积项逻辑阵列时钟（即时钟是由逻辑产生的），允许任意函数单独地钟控各个触发器。然而，当你用阵列时钟时，应仔细地分析时钟函数，以避免毛刺。通常用阵列时钟构成门控时钟。门控时钟常常同微处理器接口有关，用地址线去控制写脉冲。然而，每当用组合函数钟控触发器时，通常都存在着门控时钟。如果符合下述条件，门控时钟可以象全局时钟一样可靠地工作：驱动时钟的逻辑必须只包含一个“与”门或一个“或”门。如果采用任何附加逻在某些工作状态下，会出现竞争产生的毛刺。逻辑门的一个输入作为实际的时钟，而该逻辑门的所有其它输入必须当成地址或控制线，它们遵守相对于时

41、钟的建立和保持时间的约束。多级逻辑时钟当产生门控时钟的组合逻辑超过一级(即超过单个的“与”门或“或”门)时，证设计项目的可靠性变得很困难。即使样机或仿真结果没有显示出静态险象，但实际上仍然可能存在着危险。通常，我们不应该用多级组合逻辑去钟控PLD设计中的触发器。行波时钟另一种流行的时钟电路是采用行波时钟，即一个触发器的输出用作另一个触发器的时钟输入。如果仔细地设计，行波时钟可以象全局时钟一样地可靠工作。然而，行波时钟使得与电路有关的定时计算变得很复杂。行波时钟在行波链上各触发器的时钟之间产生较大的时间偏移，并且会超出最坏情况下的建立时间、保持时间和电路中时钟到输出的延时，使系统的实际速度下降。

42、多时钟系统许多系统要求在同一个PLD内采用多时钟。最常见的例子是两个异步微处理器器之间的接口，或微处理器和异步通信通道的接口。由于两个时钟信号之间要求一定的建立和保持时间，所以，上述应用引进了附加的定时约束条件。它们也会要求将某些异步信号同步化。在许多应用中只将异步信号同步化还是不够的，当系统中有两个或两个以上非同源时钟的时候，数据的建立和保持时间很难得到保证，我们将面临复杂的时间问题。最好的方法是将所有非同源时钟同步化。使用PLD内部的锁项环（PLL或DLL）是一个效果很好的方法，但不是所有PLD都带有PLL、DLL，而且带有PLL功能的芯片大多价格昂贵，所以除非有特殊要求，一般场合可以不使用带PLL的PLD。这时我们需要使用带使能端的D触发器，并引入一个高频时钟。