EDA技术与VHDL第一部分 VHDL语句.ppt

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1、EDA技术与VHDL,第1部分VHDL语句,一 顺序语句,1.1 赋值语句,信号赋值语句 变量赋值语句,1.2 IF语句,1.3 CASE语句,选择值|选择值,单个普通数值，如6。数值选择范围，如(2 TO 4)，表示取值为2、3或4。并列数值，如35，表示取值为3或者5。混合方式，以上三种方式的混合。,【例1】LIBRARY IEEE；USE IEEE.STD_LOGIC_1164.ALL；ENTITY mux41 IS PORT(s4，s3,s2，s1:IN STD_LOGIC;z4，z3,z2，z1:OUT STD_LOGIC);END mux41；ARCHITECTURE activ

2、OF mux41 IS SIGNAL sel:INTEGER RANGE 0 TO 15;BEGIN PROCESS(sel，s4，s3，s2，s1)BEGIN sel z1 z2 z3 z4=1;-当sel为815中任一值时选中 END CASE；END PROCESS；END activ；,一顺序语句,1.3 CASE语句,【例2】SIGNAL value:INTEGER RANGE 0 TO 15;SIGNAL out1:STD_LOGIC;.CASE value IS-缺少以WHEN引导的条件句 END CASE；.CASE value IS WHEN 0=out1 out1 out1

3、 out1=0;END CASE;,【例3】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY alu IS PORT(a,b:IN STD_LOGIC_VECTOR(7 DOWNTO 0);opcode:IN STD_LOGIC_VECTOR(1 DOWNTO 0);result:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END alu;ARCHITECTURE behave OF alu IS CONSTANT plus:STD_LOGIC_VECTOR(1

4、DOWNTO 0):=b00;CONSTANT minus:STD_LOGIC_VECTOR(1 DOWNTO 0):=b01;CONSTANT equal:STD_LOGIC_VECTOR(1 DOWNTO 0):=b10;CONSTANT not_equal:STD_LOGIC_VECTOR(1 DOWNTO 0):=b11;BEGINPROCESS(opcode,a,b)BEGIN CASE opcode IS WHEN plus=result result-a、b相等 IF(a=b)THEN result-a、b不相等 IF(a/=b)THEN result=x01;ELSE resu

5、lt=x00;END IF;END CASE;END PROCESS;END behave;,一顺序语句,1.4 LOOP语句,(1)单个LOOP语句，其语法格式如下：LOOP标号：LOOP 顺序语句 END LOOP LOOP标号;,.L2:LOOP a:=a+1;EXIT L2 WHEN a 10;-当a大于10时跳出循环 END LOOP L2;.,一顺序语句,1.4 LOOP语句,(2)FOR_LOOP语句，语法格式如下：LOOP标号：FOR 循环变量，IN 循环次数范围 LOOP 顺序语句 END LOOP LOOP标号；,一顺序语句,1.4 LOOP语句,【例4】LIBRARY I

6、EEE；USE IEEE.STD_LOGIC_1164.ALL；ENTITY p_check IS PORT(a:IN STD_LOGIC_VECTOR(7 DOWNTO 0);y:OUT STD_LOGIC);END p_check；ARCHITECTURE opt OF p_check IS SIGNAL tmp：STD_LOGIC；BEGIN PROCESS(a)BEGIN tmp=0;FOR n IN 0 TO 7 LOOP tmp=tmp XOR a(n);END LOOP;y=tmp;END PROCESS;END opt;,一顺序语句,1.4 LOOP语句,【例5】SIGNAL

7、a,b,c:STD_LOGIC_VECTOR(1 TO 3);.FOR n IN 1 To 3 LOOPa(n)=b(n)AND c(n);END LOOP;此段程序等效于顺序执行以下三个信号赋值操作：a(1)=b(1)AND c(1);a(2)=b(2)AND c(2);a(3)=b(3)AND c(3);,一顺序语句,1.5 NEXT语句,NEXT；-第一种语句格式NEXT LOOP标号；-第二种语句格式NEXT LOOP标号 WHEN 条件表达式；-第三种语句格式,【例6】.L1:FOR cnt_value IN 1 TO 8 LOOPs1:a(cnt_value):=0;NEXT WH

8、EN(b=c);s2:a(cnt_value+8):=0;END LOOP L1;,一顺序语句,1.5 NEXT语句,【例7】.L_x:FOR cnt_value IN 1 TO 8 LOOP s1:a(cnt_value):=0;k:=0;L_y:LOOP s2:b(k):=0;NEXT L_x WHEN(ef);s3:b(k+8):=0;k:=k+1;NEXT LOOP L_y;NEXT LOOP L_x;.,一顺序语句,1.6 EXIT语句,EXIT；-第一种语句格式EXIT LOOP标号；-第二种语句格式EXIT LOOP标号 WHEN 条件表达式；-第三种语句格式,一顺序语句,1.6

9、 EXIT语句,【例8】SIGNAL a,b:STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL a_less_then_b:Boolean;.a_less_then_b b EXIT;ELSIF(a(i)=0 AND b(i)=1)THEN a_less_then_b=TRUE;-a b EXIT;ELSE NULL;END IF;END LOOP;-当 i=1时返回LOOP语句继续比较,一顺序语句,1.7 WAIT语句,WAIT；-第一种语句格式WAIT ON 信号表；-第二种语句格式 WAIT UNTIL 条件表达式；-第三种语句格式WAIT FOR 时间表达式；-第

10、四种语句格式，超时等待语句,一 顺序语句,1.7 WAIT语句,【例9】SIGNAL s1,s2:STD_LOGIC;.PROCESSBEGIN.WAIT ON s1,s2；END PROCESS；,一顺序语句,1.7 WAIT语句,【例10】(a)WAIT_UNTIL结构(b)WAIT_ON结构.LOOPWait until enable=1;Wait on enable;.EXIT WHEN enable=1;END LOOP;,一顺序语句,1.7 WAIT语句,WAIT UNTIL 信号=Value；-(1)WAIT UNTIL 信号EVENT AND 信号=Value;-(2)WAIT

11、 UNTIL NOT 信号STABLE AND 信号=Value;-(3),WAIT UNTIL clock=1;WAIT UNTIL rising_edge(clock);WAIT UNTIL NOT clockSTABLE AND clock=1;WAIT UNTIL clock=1 AND clockEVENT;,一 顺序语句,1.7 WAIT语句,【例11】PROCESSBEGINWAIT UNTIL clk=1;ave=a;WAIT UNTIL clk=1;ave=ave+a;WAIT UNTIL clk=1;ave=ave+a;WAIT UNTIL clk=1;ave=(ave+a

12、)/4;END PROCESS;,一 顺序语句,1.7 WAIT语句,【例12】PROCESS BEGIN rst_loop:LOOP WAIT UNTIL clock=1 AND clockEVENT;-等待时钟信号 NEXT rst_loop WHEN(rst=1);-检测复位信号rst x=a;-无复位信号，执行赋值操作 WAIT UNTIL clock=1 AND clockEVENT;-等待时钟信号 NEXT rst_loop When(rst=1);-检测复位信号rst y=b;-无复位信号，执行赋值操作 END LOOP rs,【例13】LIBRARY IEEE;USE IEEE

13、.STD_LOGIC_1164.ALL;ENTITY shifter IS PORT(data:IN STD_LOGIC_VECTOR(7 DOWNTO 0);shift_left:IN STD_LOGIC;shift_right:IN STD_LOGIC;clk:IN STD_LOGIC;reset:IN STD_LOGIC;mode:IN STD_LOGIC_VECTOR(1 DOWNTO 0);qout:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);END shifter;ARCHITECTURE behave OF shifter IS SIGNAL enab

14、le:STD_LOGIC;BEGIN PROCESS BEGIN WAIT UNTIL(RISING_EDGE(clk);-等待时钟上升沿 IF(reset=1)THEN qout qout qout qout NULL;END CASE;END IF;END PROCESS;END behave;,一顺序语句,1.8 RETURN语句,返回语句RETURN有两种语句格式：RETURN;-第一种语句格式RETURN 表达式；-第二种语句格式,一顺序语句,1.8 RETURN语句,【例14】PROCEDURE rs(SIGNAL s,r:IN STD_LOGIC;SIGNAL q,nq:INOU

15、T STD_LOGIC)IS BEGIN IF(s=1 AND r=1)THEN REPORT Forbidden state:s and r are quual to 1;RETURN;ELSE q=s AND nq AFTER 5 ns;nq=s AND q AFTER 5 ns;END IF;END PROCEDURE rs;,一 顺序语句,1.8 RETURN语句,【例15】FUNCTION opt(a,b,opr:STD_LOGIC)RETURN STD_LOGIC IS BEGIN IF(opr=1)THEN RETURN(a AND b);ELSE RETURN(a OR b);

16、END IF;END FUNCTION opt;,一顺序语句,1.10 空操作语句,NULL;,在下例的CASE语句中，NULL用于排除一些不用的条件。CASE Opcode IS WHEN 001=tmp:=rega AND regb;WHEN 101=tmp:=rega OR regb;WHEN 110=tmp:=NOT rega;WHEN OTHERS=NULL;END CASE;,二 并行语句,并行信号赋值语句(Concurrent Signal Assignments)。进程语句(Process Statements)。块语句(Block Statements)。条件信号赋值语句(S

17、elected Signal Assignments)。元件例化语句(Component Instantiations)，其中包括类属配置语句。生成语句(Generate Statements)。并行过程调用语句(Concurrent Procedure Calls)。参数传递映射语句 端口说明语句,二 并行语句,并行语句在结构体中的使用格式如下：ARCHITECTURE 结构体名 OF 实体名 IS 说明语句 BEGIN 并行语句END ARCHITECTURE 结构体名,二 并行语句,2.1 并行信号赋值语句,1.简单信号赋值语句,赋值目标=表达式,ARCHITECTURE curt OF

18、 bc1 ISSIGNAL s1,e,f,g,h:STD_LOGIC;BEGIN output1=a AND b;output2=c+d;g=e OR f;h=e XOR f;s1=g;END ARCHITECTURE curt；,二 并行语句,2.1 并行信号赋值语句,2.条件信号赋值语句,赋值目标=表达式 WHEN 赋值条件 ELSE 表达式 WHEN 赋值条件 ELSE.表达式；,2.条件信号赋值语句,【例16】ENTITY mux IS PORT(a,b,c:IN BIT;p1,p2:IN BIT;z:OUT BIT);END;ARCHITECTURE behv OF mux IS B

19、EGIN z=a WHEN p1=1 ELSE b WHEN p2=1 ELSE c;END;,二 并行语句,二 并行语句,2.1 并行信号赋值语句,2.条件信号赋值语句,图1 例16的RTL电路图,二 并行语句,2.1 并行信号赋值语句,3.选择信号赋值语句,WITH 选择表达式 SELECT 赋值目标信号=表达式 WHEN 选择值表达式 WHEN 选择值.表达式 WHEN 选择值；,【例17】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY decoder IS PORT(a，b，

20、c:IN STD_LOGIC;data1，data2:IN STD_LOGIC;dataout:OUT STD_LOGIC);END decoder;ARCHITECTURE concunt OF decoder IS SIGNAL instruction:STD_LOGIC_VECTOR(2 DOWNTO 0)；BEGIN instruction=c,二 并行语句,2.1 并行信号赋值语句,3.选择信号赋值语句,.WITH selt SELECTmuxout=a WHEN 0|1,-0或1 b WHEN 2 TO 5,-2或3，或4或5 c WHEN 6,d WHEN 7,Z WHEN OT

21、HERS;.,二 并行语句,2.2 实体说明语句,ENTITY 实体名 IS GENERIC(参数名：数据类型);PORT(端口表);END ENTITY 实体名;,二并行语句,2.3 参数传递说明语句,GENERIC(常数名:数据类型:设定值;常数名:数据类型:设定值);,二并行语句,7.2.3 参数传递说明语句,【例18】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY andn IS GENERIC(n:INTEGER);-定义类属参量及其数据类型 PORT(a:IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);-用类属参量

22、限制矢量长度 c:OUT STD_LOGIC);END;ARCHITECTURE behav OF andn IS BEGIN PROCESS(a)VARIABLE int:STD_LOGIC;BEGIN int:=1;FOR i IN aLENGTH-1 DOWNTO 0 LOOP-循环语句 IF a(i)=0 THEN int:=0;END IF;END LOOP;c=int;END PROCESS;END;,二 并行语句,7.2.3 参数传递说明语句,【例19】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY exn IS PORT(d1,d

23、2,d3,d4,d5,d6,d7:IN STD_LOGIC;q1,q2:OUT STD_LOGIC);END;ARCHITECTURE exn_behav OF exn IS COMPONENT andn-调用例10-1的元件调用声明 GENERIC(n:INTEGER);PORT(a:IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);C:OUT STD_LOGIC);END COMPONENT;BEGIN u1:andn GENERIC MAP(n=2)-参数传递映射语句，定义类属变量，n赋值为2 PORT MAP(a(0)=d1,a(1)=d2,c=q1);u2:andn

24、 GENERIC MAP(n=5)-定义类属变量，n赋值为5 PORT MAP(a(0)=d3,a(1)=d4,a(2)=d5,a(3)=d6,a(4)=d7,c=q2);END;,二 并行语句,2.4 参数传递映射语句,GENERIC MAP(类属表),【例20】LIBRARY IEEE;-待例化元件USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_arith.ALL;USE IEEE.STD_LOGIC_unsigned.ALL;ENTITY addern IS PORT(a,b:IN STD_LOGIC_VECTOR;result:out ST

25、D_LOGIC_VECTOR);END addern;ARCHITECTURE behave OF addern IS BEGIN result=a+b;END;,二 并行语句,7.2.4 参数传递映射语句,GENERIC MAP(类属表),【例21】LIBRARY IEEE;-顶层设计USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_arith.ALL;USE IEEE.STD_LOGIC_unsigned.ALL;ENTITY adders IS GENERIC(msb_operand:INTEGER:=15;msb_sum:INTEGER:=1

26、5);PORT(b:IN STD_LOGIC_VECTOR(msb_operand DOWNTO 0);result:OUT STD_LOGIC_VECTOR(msb_sum DOWNTO 0);END adders;ARCHITECTURE behave OF adders IS COMPONENT addern PORT(a,b:IN STD_LOGIC_VECTOR;result:OUT STD_LOGIC_VECTOR);END COMPONENT;SIGNAL a:STD_LOGIC_VECTOR(msb_sum/2 DOWNTO 0);SIGNAL twoa:STD_LOGIC_V

27、ECTOR(msb_operand DOWNTO 0);BEGIN twoa twoa,b=b,result=result);U2:addern PORT MAP(a=b(msb_operand downto msb_operand/2+1),b=b(msb_operand/2 downto 0),result=a);END behave;,二并行语句,2.4 参数传递映射语句,图2 例21的RTL电路图,二 并行语句,2.5 端口说明语句,PORT(端口名:端口模式 数据类型;端口名:端口模式 数据类型);,2.6 块语句结构,块标号:BLOCK(块保护表达式)接口说明 类属说明 BEGIN

28、 并行语句END BLOCK 块标号;,【例22】.ENTITY gat IS GENERIC(l_time:TIME;s_time:TIME);-（参数传递）类属说明 PORT(b1,b2,b3:INOUT BIT);-结构体全局端口定义 END ENTITY gat;ARCHITECTURE func OF gat IS SIGNAL a1:BIT;-结构体全局信号 a1定义 BEGINBlk1:BLOCK-块定义，块标号名是blk1 GENERIC(gb1,gb2:Time);-定义块中的局部类属参量 GENERIC MAP(gb1=l_time,gb2=s_time);-局部端口参量设

29、定 PORT(pb:IN BIT;pb2:INOUT BIT);-块结构中局部端口定义 PORT MAP(pb1=b1,pb2=a1);-块结构端口连接说明 CONSTANT delay:Time:=1 ms;-局部常数定义 SIGNAL s1:BIT;-局部信号定义 BEGIN s1=pb1 AFTER delay;pb2=s1 AFTER gb1,b1 AFTER gb2;END BLOCK blk1;END ARCHITECTURE func;,二 并行语句,2.6 块语句结构,【例23】.b1:BLOCK SIGNAL s1:BIT;BEGIN S1=a AND b;b2:BLOCK

30、SIGNAL s2:BIT;BEGIN s2=c AND d;b3:BLOCK BEGIN Z=s2;END BLOCK b3;END BLOCK b2;y=s1;END BLOCK b1;.,【例24】LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;ENTITY f_adder IS PORT(ain,bin,cin:IN std_logic;sum,cout:OUT std_logic);END f_adder;ARCHITECTURE e_ad OF f_adder IS SIGNAL so1,co1,co2:std_logic;BEGIN h_adde

31、r1:BLOCK-半加器u1 BEGIN PROCESS(ain,bin)BEGIN so1=NOT(ain XOR(NOT bin);co1=ain AND bin;END PROCESS;END BLOCK h_adder1;h_adder2:BLOCK-半加器u2 SIGNAL so2:std_logic;BEGIN so2=NOT(so1 XOR(NOT cin);co2=so1 and cin;sum=so2;END BLOCK h_adder2;or2:BLOCK-或门u3 BEGIN PROCESS(co2,co1)BEGIN cout=co2 OR co1;END PROCES

32、S;END BLOCK or2;END e_ad;,二 并行语句,2.6 块语句结构,图3 例24的RTL电路图,二并行语句,2.7 元件例化语句,COMPONENT 元件名 IS GENERIC(类属表)；-元件定义语句 PORT(端口名表)；END COMPONENT 文件名；例化名：元件名 PORT MAP(-元件例化语句 端口名=连接端口名，.)；,二 并行语句,2.8 生成语句,标号：FOR 循环变量 IN 取值范围 GENERATE 说明 BEGIN 并行语句 END GENERATE 标号；或 标号：IF 条件GENERATE 说明 Begin 并行语句 END GENERATE

33、 标号；,二 并行语句,表达式 TO 表达式;-递增方式，如1 TO 5表达式 DOWNTO 表达式;-递减方式，如5 DOWNTO 1,【例25】.COMPONENT compPORT(x:IN STD_LOGIC；y:OUT STD_LOGIC);END COMPONENT;SIGNAL a:STD_LOGIC_VECTOR(0 TO 7)；SIGNAL b:STD_LOGIC_VECTOR(0 TO 7)；.gen:FOR i IN aRANGE GENERATE u1:comp PORT MA(x=a(i)，y=b(i);END GENERATE gen,.,2.8 生成语句,二 并行

34、语句,图4 生成语句产生的8个相同的电路模块,2.8 生成语句,二 并行语句,【例26】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY Latch IS PORT(D，ENA:IN STD_LOGIC;Q:OUT STD_LOGIC);END ENTITY Latch;ARCHITECTURE one OF Latch IS SIGNAL sig_save:STD_LOGIC;BEGIN PROCESS(D,ENA)BEGIN IF ENA=1 THEN sig_save=D;END IF;Q=sig_save;END PROCESS;END A

35、RCHITECTURE one;,2.8 生成语句,【例27】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SN74373 IS PORT(D:IN STD_LOGIC_VECTOR(8 DOWNTO 1);OEN,G:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(8 DOWNTO 1);END ENTITY SN74373;ARCHITECTURE two OF SN74373 IS SIGNAL sigvec_save:STD_LOGIC_VECTOR(8 DOWNTO 1);BEGIN PROCESS(D,OEN

36、,G,sigvec_save)BEGIN IF OEN=0 THEN Q=sigvec_save;ELSE Q=ZZZZZZZZ;END IF;IF G=1 THEN Sigvec_save=D;END IF;END PROCESS;END ARCHITECTURE two;ARCHITECTURE one OF SN74373 IS COMPONENT Latch PORT(D,ENA:IN STD_LOGIC;Q:OUT STD_LOGIC);END COMPONENT;SIGNAL sig_mid:STD_LOGIC_VECTOR(8 DOWNTO 1);BEGIN GeLatch:FO

37、R iNum IN 1 TO 8 GENERATE Latchx:Latch PORT MAP(D(iNum),G,sig_mid(iNum);END GENERATE;Q=sig_mid WHEN OEN=0 ELSE ZZZZZZZZ;-当OEN=1时，Q(8)Q(1)输出状态呈高阻态END ARCHITECTURE one;,【例28】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY d_ff ISPORT(d,clk_s:IN STD_LOGIC;q:OUT STD_LOGIC;nq:OUT STD_LOGIC);END ENTITY d_

38、ff;ARCHITECTURE a_rs_ff OF d_ff ISBEGINbin_p_rs_ff:PROCESS(CLK_S)BEGIN IF clk_s=1 AND clk_sEVENT THEN q=d;nq=NOT d;END IF;END PROCESS;END ARCHITECTURE a_rs_ff;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY cnt_bin_n isGENERIC(n:INTEGER:=6);PORT(q:OUT STD_LOGIC_VECTOR(0 TO n-1);in_1:IN STD_LOGIC);EN

39、D ENTITY cnt_bin_n;ARCHITECTURE behv OF cnt_bin_n ISCOMPONENT d_ff PORT(d,clk_s:IN STD_LOGIC;Q,NQ:OUT STD_LOGIC);END COMPONENT d_ff;SIGNAL s:STD_LOGIC_VECTOR(0 TO n);BEGIN s(0)=in_1;q_1:FOR i IN 0 TO n-1 GENERATE dff:d_ff PORT MAP(s(i+1),s(I),q(i),s(i+1);END GENERATE;END ARCHITECTURE behv;,二 并行语句,图5

40、 6 位二进制计数器原理图,2.8 生成语句,二 并行语句,2.9 REPORT语句,【例29】LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;ENTITY RSFF2 IS PORT(S,R:IN std_logic;Q,QF:OUT std_logic);END RSFF2;ARCHITECTURE BHV OF RSFF2 IS BEGIN P1:PROCESS(S,R)VARIABLE D:std_logic;BEGIN IF R=1 and S=1 THEN REPORT BOTH R AND S IS 1;-报告出错信息 ELSIF R=1 and

41、 S=0 THEN D:=0;ELSIF R=0 and S=1 THEN D:=1;END IF;Q=D;QF=NOT D;END PROCESS;END BHV;,二 并行语句,2.10 断言语句,ASSERT REPORT SEVERITY；,表1 预定义错误等级,二 并行语句,1.顺序断言语句,【例30】P1:PROCESS(S,R)VARIABLE D:std_logic;BEGINASSERT not(R=1and S=1)REPORT both R and S equal to 1 SEVERITY Error;IF R=1 and S=0 THEN D:=0;ELSIF R=0

42、 and S=1 THEN D:=1;END IF;Q=D;QF=NOT D;END PROCESS;,2.10 断言语句,2.并行断言语句,【例31】LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;ENTITY RSFF2 IS PORT(S,R:IN std_logic;Q,QF:OUT std_logic);END RSFF2;ARCHITECTURE BHV OF RSFF2 IS BEGIN PROCESS(R,S)BEGIN ASSERT not(R=1and S=1)REPORT both R and S equal to 1 SEVERITY

43、Error;END PROCESS;PROCESS(R,S)VARIABLE D:std_logic:=0;BEGIN IF R=1 and S=0 THEN D:=0;ELSIF R=0 and S=1 THEN D:=1;END IF;Q=D;QF=NOT D;END PROCESS;END;,三 属性描述与定义语句,1.信号类属性,(NOT clockSTABLE AND clock=1)(clockEVENT AND clock=1),2.数据区间类属性,.SIGNAL range1:IN STD LOGIC VECTOR(0 TO 7)；.FOR i IN range1RANGE L

44、OOP.,三属性描述与定义语句,3.数值类属性,.PROCESS(clock,a,b);TYPE obj IS ARRAY(0 TO 15)OF BIT;SIGNAL ele1,ele2,ele3,ele4:INTEGER;BEGIN ele1=objRIGNT;ele2=objLEFT;ele3=objHIGH;ele4=objLOW;.,三属性描述与定义语句,3.数值类属性,LIBRARY IEEE;-PARITY GENERATORUSE IEEE.STD_LOGIC_1164.ALL;ENTITY parity IS GENERIC(bus_size:INTEGER:=8);PORT(

45、input_bus:IN STD_LOGIC_VECTOR(bus_size-1 DOWNTO 0);even_numbits,odd_numbits:OUT STD_LOGIC);END parity;ARCHITECTURE behave OF parity ISBEGINPROCESS(input_bus)VARIABLE temp:STD_LOGIC;BEGIN temp:=0;FOR i IN input_busLOW TO input_busHIGH LOOPtemp:=temp XOR input_bus(i);END LOOP;odd_numbits=temp;even_num

46、bits=NOT temp;END PROCESS;END behave;,三属性描述与定义语句,4.数组属性LENGTH,.TYPE arry1 ARRAY(0 TO 7)OF BIT；VARIABLE wth:INTEGER;.wth1:=arry1LENGTH;-wth1=8.,三属性描述与定义语句,5.用户定义属性,ATTRIBUTE 属性名:数据类型;ATTRIBUTE 属性名 OF 对象名:对象类型IS 值;,LIBRARY synplify;USE synplicity.attributes.all;,三属性描述与定义语句,5.用户定义属性,LIBRARY IEEE;USE IE

47、EE.STD_LOGIC_1164.ALL;ENTITY cntbuf IS PORT(Dir:IN STD_LOGIC;Clk,Clr,OE:IN STD_LOGIC;A,B:INOUT STD_LOGIC_VECTOR(0 to 1);Q:INOUT STD_LOGIC_VECTOR(3 downto 0);ATTRIBUTE PINNUM:STRING;ATTRIBUTE PINNUM OF Clk:signal is 1;ATTRIBUTE PINNUM OF Clr:signal is 2;ATTRIBUTE PINNUM OF Dir:signal is 3;ATTRIBUTE P

48、INNUM OF OE:signal is 11;ATTRIBUTE PINNUM OF Q:signal is 17,16,15,14;END cntbuf;,MajpjMVcyzj21HLfrvy96dv02lPPfYgxUS7IYmZkyEmZ0kGeYZS3bpLCkYH1lt4EK7CxmUX3ijoYSOer7ZuaVWYgz4EpZrUirVpMzzvNtf1XZw5oswSXOtFaejnOcmfE1lZgnN1RSXg8wLCG8CVQ3XPJMvodPFWcpiYJgZazNSEPNIaklYSu7qSd1UpaxmZDlpN9zW7kljfsLCLi26Yv109ffbn

49、DH8LbUN1G6ACURQ39eG12KHL9tXsZ1jzgoCK8g1kuNOh5eFvcmVT5ZYVQt9zk3rp3qLnf02FovEXxVRxjCcFRNppiJljNiOuk6fONnyX7fyGg7sXZ49BmCN5oy9VesHpKzdjTKwjrkCEQCFDehVmGax3lrOEbw63VscA3YSijtUKoCyiLzAlVRp7l4QgPNHxvJFFDyjUVN3oHlMah0XBd4uTbkfPIhHtw0evPmYOrdhEDoPwvYhzlGplU1AU9mpyiCXH8gpPCBRYjq77VcnbXumNE1yGfyTsbSj89J63kRTK

50、DkKUg3mdS5sJ4X5cQ8dK7oW9IkScssECQdz2O9UTlpRjAFPChjhLdzopQzwxQf8ozdzOhogwAooXpUF83BX4C3jRgjDJiiXEUDMaNz4vQ4n164vspddHvOIVuBBdMA4xp1YhiHk0vOJ8TL1BxogzVlMpmod6ianYGmksQq6NWCEd56hZF4wfaNyZcrGfNxnPiG6ZAxSkfmhJAKtNmCqbRmppeXp8inz4eq3HkWCMSORyMMX522xpHG6basNr6KQfbZsFbHjzyNlJrruLolKFcC84dqfijBO5Dy2NaBcNEBPg