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1、(1),1,Using the MAX II ParallelFlash Loader with theQuartus II Software,May 2005,ver.1.0Introduction,Application Note 386With the density of FPGAs increasing,the need for larger configurationstorage is also increasing.If the user system already contains a commonflash interface(CFI)flash memory,it ca

2、n be utilized for the FPGAconfiguration storage.The MAX II parallel flash loader(PFL)feature inMAX II devices provides an easy way to program CFI flash memorydevices through the Joint Test Action Group(JTAG)interface,and thelogic to control configuration from the flash memory device to the AlteraFPG

3、A.Figure 1 shows the PFL feature.Figure 1.MAX II PFL FeaturePassive,JTAG,Serial,Interface,MAX II CPLD,Interface,AlteraFPGA,CommonFlashInterfaceCFI FlashMemory(1)Note to Figure 1:The Quartus II software version 5.0 supports Intel-based C3 CFI flash devices.Referto Table 1 for the list of supported de

4、vices.Future versions of the Quartus IIsoftware will support more types of CFI flash devices.,MAX II PFL,Two functions of the MAX II PFL feature are:,Programming the CFI flash device through the MAX II JTAGinterfaceControlling the configuration of the FPGA from the CFI flash dataFor the first functi

5、on,the MAX II device operates as the bridge betweenthe JTAG interface and the CFI flash memory parallel address/datainterface.Altera configuration devices support programming throughthe JTAG interface,allowing for in-system programming and updates.Altera Corporation,AN-386-1.0,Preliminary,2,Using th

6、e MAX II Parallel Flash Loader with the Quartus II SoftwareStandard flash memory devices,however,do not support the JTAGinterface and therefore do not support direct programming throughJTAG.With the MAX II device,you can use its JTAG interface to indirectlyprogram the flash memory.The MAX II JTAG bl

7、ock interfaces directlywith the logic array when in a special non-test JTAG mode.This modebrings the JTAG chain through the logic array instead of the MAX IIboundary scan cells.The PFL feature provides the JTAG interface logic toconvert the JTAG stream provided by the Quartus II software andprogram

8、CFI flash memory devices connected to the MAX II I/O pins.Figure 2 shows the MAX II device acting as the bridge to program theflash memory through the JTAG interface.Figure 2.Programming the Flash Memory through the JTAG Interface,JTAG,MAX II CPLD,Configuration Data,Interface,AlteraFPGA,PFLCommonFla

9、shInterfaceCFI FlashMemoryThe second function of the MAX II device is to control the configurationof Altera FPGAs.Unlike dedicated Altera configuration devices,the flashmemory device only stores configuration data and does not have thebuilt-in logic to control the FPGA configuration process.The PFLm

10、egafunction logic within the MAX II device determines when to startthe configuration process,reading the data from the flash memory andconfiguring the Altera FPGA accordingly.Figure 3 shows the MAX IIdevice as the configuration controller for the FPGA.Altera CorporationPreliminary,8,(1),(2),(3),3,Qu

11、artus II SupportFigure 3.FPGA Configuration with Flash Memory DataPassive,MAX II CPLD,Serial,InterfacePFLCommonFlashInterfaceCFI FlashMemory,AlteraFPGA,Quartus IISupport,The Quartus II software generates the MAX II PFL megafunction logic forthe programming bridge and configuration.User entry of SRAM

12、 ObjectFiles(.sof)and hexadecimal files(.hex)in the Quartus II software creates,the programming file for the flash memory.Table 1 shows the types offlash memory,data width,configuration mode,and file formatsupported.Future versions of the Quartus II software will support moretypes of CFI flash memor

13、y,data widths,configuration modes,and fileformats.Table 1.Flash Memory,Configuration Mode&File Format Supported by the PFL Feature in the Quartus IISoftware,Flash Memory SupportedManufacturer Device Name Density(Mbit),Data Width,ConfigurationMode(1),File Format(2),Intel,28F800C3,16 bit,Passive Seria

14、l,POF(3),28F160C328F320C328F640C3,163264,Notes to Table 1:Configuration of an Altera FPGA by the MAX II device through the PFL.Supported file format to program the MAX II device and the flash memory device.Programmer Object File(.pof).HEX file format is allowed for non-configuration data storage.Alt

15、era CorporationPreliminary,(1),4,Using the MAX II Parallel Flash Loader with the Quartus II SoftwareTable 2 shows the PFL megafunction logic element(LE)resource usagefor different density CFI flash memories.,Table 2.LE Usage for PFL Megafunction,Note(1),Flash SupportedDevice,CFI_8Mb,CFI_16Mb,CFI_32M

16、b,CFI_64Mb,EPM240EPM570EPM1270EPM2210,223238238238,227242242242,231246246246,235250250250,Note to Table 2:LE usage based on a compiled PFL megafunction design in the Quartus II software version 5.0.Page Mode ImplementationThe PFL allows the storage of configuration data up to a maximum ofeight diffe

17、rent pages in a CFI flash memory block.A single page is usedto configure a single FPGA chain that can contain more than one FPGA(i.e.,multiple SOFs can be stored in a single page).The start address foreach page resides on an 8-Kbyte boundary.The first valid start address is0 x000000,the next valid s

18、tart address must be an increment of 0 x2000.When converting the SOF(s)to a POF,you can either specify the start andend address for the page,specify only the start address,or allow theQuartus II software to automatically determine the address.The option bits sector stores the start address for each

19、page and theprogram done bits,indicating whether each page is successfullyprogrammed.You can store the option bits in the unused addresslocations in the flash memory.You need to specify the start address for theoption bit sector when converting the SOF(s)to the POF,as well as whencreating the PFL me

20、gafunction.This procedure is covered later in the“Instantiating the PFL Megafunction in the Quartus II Software”and“Converting the SOF(s)to a POF for the Flash Device”sections.Figure 4 shows the page mode and option bits implementation in the CFIflash memory.Altera CorporationPreliminary,(1),(2),5,I

21、nput/Output Signals for the PFLFigure 4.Page Mode&Option Bits Implementation in the Flash Memory8 BitsEnd Address(1)Option Bits(2)Configuration Data(Page 2)Configuration Data(Page 1)Page 2 Address+Program DonePage 1 Address+Program Done,Configuration Data(Page 0),Page 0 Address+Program Done,0 x00000

22、0Note to Figure 4:The end address depends on the density of the flash device.The following lists thedevice density together with the end address respectively:8 Mbits:0 x0FFFFF,16 Mbits:0 x1FFFFF,32 Mbits:0 x3FFFFF,and 64 Mbits:0 x7FFFFF.You specify the byte address location for the option bits secto

23、r.Bit 0 up to Bit 11 for the page start address are all zeros and are not storedas option bits.Figure 5 shows how the start address and program done bitfor each page is stored in the option bits sector.Figure 5.Page Start Address&Program Done Bit Stored as Option Bits,Bit 7.Bit 1,Bit 0,0X002001,Page

24、 Start Address 18:12Bit 7.Bit 0,ProgramDone,0X002000,Page Start Address 26:19,Input/OutputSignals for the,This section explains the input/output signals of the PFL megafunction.Figure 6 shows the PFL megafunction symbol.,PFLAltera CorporationPreliminary,f,Input,6,Using the MAX II Parallel Flash Load

25、er with the Quartus II SoftwareFigure 6.PFL Megafunction SymbolTable 3 describes the functions of the PFL signals and specifies theexternal pull-up resistor required for the configuration pins.For pull-up information on configuring pins for specific Altera FPGAfamilies,refer to the Configuration Han

26、dbook.Table 3.PFL Signals(Part 1 of 2),clk_in,Pin,DescriptionInput,Weak Pull-Up/Pull-Down,FunctionUser input clock for the device.The frequency,should be same as specified in themegafunction and should not be higher than themaximum DCLK frequency acceptable by theFPGA during configuration.(1),nreset

27、fpga_page_select2.0,Input,Reset pin for the PFL.Pulled high to enable thePFL.Otherwise,should be pulled low any timethe PFL is unused.Determines the page to be used for theconfiguration.,fpga_conf_done,Input,10-k Pull-UpResistor,Connects to the CONF_DONE pin of the FPGA.The FPGA releases the pin hig

28、h when,configuration is successful.,fpga_serial_out,Output,10-k Pull-Down Resistor,Connects to the DATA0 pin of the FPGA.Thispin transmits serial flash memory data from the,MAX II device to the FPGA duringconfiguration.,fpga_dclkfpga_nstatus,OutputInput/Output,10-k Pull-Down Resistor10-k Pull-UpResi

29、stor,Connects to the DCLK pin of the FPGA.Clockinput to the FPGA device during configuration.Connects to the nSTATUS pin of the FPGA.TheFPGA pulls this pin low if a configuration error,occurs.Altera CorporationPreliminary,Input/,(1),7,Input/Output Signals for the PFLTable 3.PFL Signals(Part 2 of 2),

30、Pinfpga_ninit_conf,DescriptionOutput,Weak Pull-Up/Pull-Down10-k Pull-UpResistor,FunctionConnects to the nCONFIG pin of the FPGA.Alow pulse resets the FPGA and initiates,configuration.,flash_readyflash_addrmax.0,InputOutput,Used for system-level synchronization.This pincan be driven by a processor or

31、 any arbitratorwho controls access to the flash.The PFL willnot drive the flash interface until this pin is low.If you want the PFL to always access the flash,pull this pin low.Address inputs for memory addresses.Themost significant bit(MSB)depends on thedensity of the flash device.8 Mbits:1816 Mbit

32、s:1932 Mbits:2064 Mbits:21,flash_data15.0,Output,Data bus to receive/transmit 16-bit data to/fromthe flash memory in parallel.,flash_nweflash_nceflash_noeflash_request,OutputOutputOutputOutput,Connects to the WE pin of the flash device.Alow signal enables write operation to the flashdevice.Connects

33、to the CE pin of the flash device.Alow signal enables the flash device.Connects to the OE pin of the flash device.Alow signal enables the flash devices outputsduring a read operation.Used for system-level synchronization.This pin,should be connected to a processor orarbitrator if needed.The PFL driv

34、es this pinhigh when it needs to access the flash.Theprocessor or arbitrator controls theflash_ready input,allowing the PFL toaccess the flash.Note to Table 3:Refer to the Configuration Handbook for FPGA configuration maximum DCLK frequencies.Altera CorporationPreliminary,1.,2.,3.,(1),8,Using the MA

35、X II Parallel Flash Loader with the Quartus II Software,Using the PFL inthe Quartus IISoftware,This section describes the steps for using the PFL feature with theQuartus II software.The process includes:The instantiation of the PFL megafunction in the user design,Converting the SOF(s)that contains t

36、he configuration data for theAltera FPGA to a POF specifically for the flash deviceProgramming the POF into the flash device through the MAX IIdevice using the Quartus II programmerFigure 7 shows the steps for using the PFL.The Quartus II software doesnot support simulation of JTAG pins or the progr

37、amming process of theMAX II or flash device.Figure 7.Quartus II PFL StepsCreate a New Project,Instantiate the PFL Megafunction in,the MAX II Design&Make Pin Assignments,Compile&Obtain,Altera FPGASOF(s)Compile,&Obtain,(1),Add SOF(s)for Conversion to POF,MAX IIPOFConvert to,Add MAX II POF toQuartus II

38、 Programmer,POF forTargetedFlash,Attach Flash POF to the MAX IIPOF in the Quartus II ProgrammerProgram the MAX II and Flash DeviceMAX II Configures the FPGA withConfiguration Data from the Flash DeviceNote to Figure 7:Jam(.jam)or Jam Byte-Code File(.jbc)format will be supported in future versions of

39、 the Quartus II software.Altera CorporationPreliminary,1.,2.,3.,4.,5.,9,Using the PFL in the Quartus II Software,Instantiating the PFL Megafunction in the Quartus II Software,Perform the following steps to generate a PFL megafunction,instantiation.You should then instantiate the megafunction in your

40、MAX II top-level design.,Choose MegaWizard Plug-In Manager(Tools menu).,In the dialog box that appears,select Create a new custommegafunction variation and click Next.,Select the Hardware Description Language(HDL)output file typeand name the file.Click Next(Verilog HDL was chosen for thisexample).Af

41、ter making these settings,the dialog box appears,asshown in Figure 8.,Select Parallel Flash Loader.,Specify the directory and output filename.Click Next.,Figure 8.Selecting the PFL Megafunction,Altera Corporation,Preliminary,6.,7.,Using the MAX II Parallel Flash Loader with the Quartus II SoftwareSp

42、ecify the clock frequency,the Intel CFI flash device and density,and the address for the option bits,as shown in Figure 9.The clockis the user-supplied clock frequency used by the megafunction toconfigure the FPGA and should not exceed the maximum clock(DCLK)frequency acceptable by the FPGA for conf

43、iguration.Theaddress is the starting address where the option bits are stored inthe flash memory and should be on a 8-Kbyte boundary.Click Next.Figure 9.The PFL Megafunction SettingsFigure 10 shows the files that can be created for the megafunction.Choose the additional file type that you want to cr

44、eate and clickFinish.The Quartus II software generates the PFL megafunction inthe form of the HDL file you specified as well as any additional files(if specified).,10Preliminary,Altera Corporation,1.,2.,Using the PFL in the Quartus II SoftwareFigure 10.Selecting the Type of Output File for the PFL M

45、egafunctionConverting the SOF(s)to a POF for the Flash DeviceUse the generated FPGA device SOF(s)to create the flash device POF.Youcan also add in other non-configuration data into the POF by selecting theHEX file that contains your user data when creating the flash device POF.Choose Convert Program

46、ming Files(File menu).As shown in Figure 11,under programming file type,specifyProgrammer Object File(.pof)and name the file accordingly.,Altera Corporation,11Preliminary,3.,4.,Using the MAX II Parallel Flash Loader with the Quartus II SoftwareFigure 11.The Convert Programming File MenuSelect the CF

47、I device with the correct density for the configurationdevice(e.g.,CFI_32Mb means CFI device with 32-Mbit capacity).To add in the configuration data,select SOF Data under Input filesto convert.Click Add File and browse to the SOFs you want to add.You can place more than one SOF into the same page if

48、 you intend toconfigure a chain of FPGAs.The order of the SOFs should follow theorder of the devices in the chain.If you want to store the data from another SOF in another page,clickAdd Data.Add the SOF(s)to that new page.To set the page number and name,select SOF Data and click Properties.Figure 12

49、 shows the SOF Data Properties dialog box.,12Preliminary,Altera Corporation,5.,6.,7.,8.,Using the PFL in the Quartus II SoftwareFigure 12.SOF Data PropertiesUnder Address mode for selected pages,select Auto to let theQuartus II software automatically set the start address for that page.Select Block

50、to specify the start and end address,or select Start tospecify the start address only.Click OK.You can also store user data(HEX file format)in the flash device.Select Main Block Data in the Convert Programming Files windowshown in Figure 11 and click Add File.Select the HEX file thatcontains the use