数字电路设计ppt课件 第9讲 互连.ppt

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1、数字集成电路,第九讲 互连问题,互连参数的影响,降低可靠性,影响性能 增加延时 增加功耗,参数的分类,电容,电阻,电感,9.2 INTERCONNECT,Dealing with Capacitance,9.2.1电容串扰效应,电容串扰效应动态节点,3 x 1 mm overlap:0.19 V disturbance,C,Y,C,XY,V,DD,PDN,CLK,CLK,In,1,In,2,In,3,Y,X,2.5 V,0 V,电容串扰效应被驱动节点,tXY=RY(CXY+CY),Keep time-constant smaller than rise time,V(Volt),0,0.5,0

2、.45,0.4,0.35,0.3,0.25,0.2,0.15,0.1,0.05,0,1,0.8,0.6,t(nsec),0.4,0.2,X,Y,V,X,R,Y,C,XY,C,Y,tr,克服电容串扰的方法,避免浮空节点对串扰敏感的节点，如预充电总线等，应当增加保持器件以降低阻抗敏感节点应当很好地与全摆幅信号隔离在满足时序约束的范围内尽可能加大上升（下降）时间这会对短路功耗有影响在敏感的低摆幅布线网络中采用差分信号传输方法，使串扰信号变为不会影响电路工作的共模干扰信号同一层上的两条导线平行走线的距离不要太长，减小线间电容两个信号之间增加屏蔽线，能有效地使线间电容变为一个接地电容，从而消除干扰不同层

3、上信号之间的线间电容可以通过增加额外的布线层来进一步减小,屏蔽,GND,GND,屏蔽线,衬底(,GND,),屏蔽层,V,DD,9.2.2串扰与性能,Cc,-当相邻的信号线向相反的方向翻转时，延时增加延时依赖于相邻信号线的活动,Miller 效应-Both terminals of capacitor are switched in opposite directions(0 Vdd,Vdd 0)-Effective voltage is doubled and additional charge is needed(from Q=CV),串扰对延时的影响,r is ratio between

4、capacitance to GND and to neighbor,在最坏情况下，g5，表明仅仅由于线上翻转方向的影响，导线延时和最好情形之间就可以有500的差别！,tp,k=gCw(0.38Rw+0.69RD)Cw=cwL;Rw=rwL,解决方法（I）,估计和改进：经过细致的参数提取和模拟可以确定延时的瓶颈，然后对电路进行适当的修改最常使用的方法。缺点：在整个设计生产过程中需要多次的反复，费时能动性的版图生成：在导线的布线程序中考虑相邻导线的影响，以保证满足性能方面的要求很有吸引力但是所要求的EDA工具非常复杂,解决方法（2）,可预测的结构：使用预先定义的、已知的或保守的布线结构，保证电路

5、既能满足设计者提出的技术要求，又能使串扰不会引起失效密集型布线结构避免最坏情形的产生编解码技术,结构化可预测的连线结构,Example:Dense Wire Fabric(Sunil Kathri)Trade-off:线间串扰电容小了40倍，代价：2%的延时开销，5的面积和总电容开销Also:FPGAs,VPGAs,数据编码消除最恶劣情形,Encoder,Decoder,Bus,In,Out,电容负载和电路性能,复杂的设计中单个门常常需要驱动很大的扇出，因而具有很大的电容负载总线、时钟网络、全局控制信号（set/reset)存储器中的读写信号最坏情形发生在芯片内外接口，此时负载有封装导线、印刷

6、电路板导线、连接的器件的输入电容组成片外负载可以大至50pF，是标准片上负载的数千倍,驱动大电容负载,Transistor Sizing Cascaded Buffers,使用级联缓冲器,CL=20 pF,In,Out,1,2,N,0.25 mm processCin=2.5 fFtp0=30 ps,F=CL/Cin=8000fopt=3.6 N=7tp=0.97 ns,(See Chapter 5),输出缓冲器设计,Transistor Sizes for optimally-sized cascaded buffer tp=0.97 ns,0.25 mm process,CL=20 pF,

7、需要一些栅极宽度大约为1.5mm的超大晶体管！无法接受，因为一个复杂芯片需要很多这样的驱动器！,解决方法,在大多数情况下并不需要达到最优的缓冲器延时。片外通信常常能以片上时钟速度的几分之一进行。放宽延时要求仍然可以使片外时钟速度超过100MHz，但却大大降低了对缓冲的要求。,Delay as a Function of F and N,10,1,3,5,7,Number of buffer stages N,9,11,10,000,1000,100,t,p,/,t,p,0,F,=,100,F,=,1000,F,=,10,000,tp/tp0,输出驱动设计,Trade off Performan

8、ce for Area and EnergyGiven tpmax find N and fAreaEnergy,选择较大的f有助于减小面积,输出驱动器设计再次考虑,Transistor Sizes of redesigned cascaded buffer tp=1.89 ns,大尺寸晶体管的实现,G(ate),S(ource),D(rain),Multiple,Contacts,small transistors in parallel,Reduces diffusion capacitanceReduces gate resistance,大尺寸晶体管意味着很长的栅极连线，而较长的多晶硅

9、线具有较高的电阻，从而降低了开关性能,Bonding Pad Design,Bonding Pad,Out,In,VDD,GND,100 mm,GND,Out,ESD Protection,When a chip is connected to a board,there is unknown(potentially large)static voltage differenceEqualizing potentials requires(large)charge flow through the padsDiodes sink this charge into the substrate n

10、eed guard rings to pick it up.,ESD Protection,芯片封装,Bond wires(25m)are used to connect the package to the chip Pads are arranged in a frame around the chip Pads are relatively large(100m in 0.25m technology),with large pitch(100m)Many chips areas are pad limited,Pad Frame,Layout,Die Photo,驱动器电路,An al

11、ternative is flip-chip:Pads are distributed around the chipThe soldering balls are placed on padsThe chip is flipped onto the packageCan have many more pads,三态缓冲,互连,Dealing with Resistance,9.3电阻效应的影响,We have already learned how to drive RC interconnectImpact of resistance is commonly seen in power s

12、upply distribution:IR dropVoltage variationsPower supply is distributed to minimize the IR drop and the change in current due to switching of gates,9.3.1 RI Introduced Noise,电源/地分布,使用第三层金属走电源/地(EV4),在EV4设计中，增加了又厚又宽的第三层金属线Power supplied from two sides of the die via 3rd metal layer2nd metal layer use

13、d to form power grid90%of 3rd metal layer used for power/clock routing,Metal 3,Metal 2,Metal 1,Courtesy Compaq,4层金属方法(EV5)3,4层用于电源/地的走线,4th“coarse and thick”metal layer added to thetechnology for EV5 designPower supplied from four sides of the dieGrid strapping done all in coarse metal90%of 3rd and

14、4th metals used for power/clock routing,Metal 3,Metal 2,Metal 1,Metal 4,Courtesy Compaq,2 reference plane metal layers added to thetechnology for EV6 designSolid planes dedicated to Vdd/VssSignificantly lowers resistance of gridLowers on-chip inductance,6 层金属方法 EV6,Metal 4,Metal 2,Metal 1,RP2/Vdd,RP

15、1/Vss,Metal 3,Courtesy Compaq,电阻与功耗分布问题,Source:Cadence,Requires fast and accurate peak current prediction Heavily influenced by packaging technology,Before,After,9.3.2 Electromigration(1)电迁移,Electromigration(2),电迁移的发生率取决于温度、晶体结构和平均电流密度。其中在设计中，只有平均电流密度可控。通常使电流保持在低于0.51mA/um可以防止电迁移。,9.3.3 Resistivity

16、and Performance,Diffused signal propagationDelay L2,CN-1,CN,C2,R1,R2,C1,Tr,Vin,RN-1 RN,The distributed rc-line,The Global Wire Problem,Challenges精确的同步和正确的操作设计技术新互连材料插入中继器优化互连结构,Interconnect ProjectionsLow-k dielectrics,Both delay and power are reduced by dropping interconnect capacitanceTypes of low

17、-k materials include:inorganic(SiO2),organic(Polyimides)and aerogels(ultra low-k),Interconnect Projections:Copper,Copper is planned in full sub-0.25 mm process flows and large-scale designs(IBM,Motorola,IEDM97)With cladding and other effects,Cu 2.2 mW-cm vs.3.5 for Al(Cu)40%reduction in resistanceEl

18、ectromigration improvement;100X longer lifetime(IBM,IEDM97)Electromigration is a limiting factor beyond 0.18 mm if Al is used(HP,IEDM95),Vias,Diagonal Wiring,y,x,destination,Manhattan,source,diagonal,20+%Interconnect length reduction Clock speed Signal integrity Power integrity 15+%Smaller chips plu

19、s 30+%via reduction,Courtesy Cadence X-initiative,Using Bypasses,Driver,Polysilicon word line,Polysilicon word line,Metal word line,Metal bypass,Driving a word line from both sides,Using a metal bypass,WL,WL,K,cells,Reducing RC-delay,Repeater,(chapter 5),Repeater Insertion(Revisited),Taking the repe

20、ater loading into account,For a given technology and a given interconnect layer,there exists an optimal length of the wire segments between repeaters.The delay of these wire segments is independent of the routing layer!,9.4 INTERCONNECT,Dealing with Inductance,SKIPPED,The“Network-on-a-Chip”,L di/dt,

21、Impact of inductance on supply voltages:Change in current induces a change in voltage Longer supply lines have larger L,L di/dt:Simulation,Input rise/fall time:50 psec,Input rise/fall time:800 psec,decoupled,Without inductors,With inductors,Dealing with Ldi/dt,Separate power pins for I/O pads and ch

22、ip core.Multiple power and ground pins.Careful selection of the positions of the power and ground pins on the package.Increase the rise and fall times of the off-chip signals to the maximum extent allowable.Schedule current-consuming transitions.Use advanced packaging technologies.Add decoupling cap

23、acitances on the board.Add decoupling capacitances on the chip.,Choosing the Right Pin,Decoupling Capacitors,Decoupling capacitors are added:on the board(right under the supply pins)on the chip(under the supply straps,near large buffers),De-coupling Capacitor Ratios,EV4total effective switching capa

24、citance=12.5nF128nF of de-coupling capacitancede-coupling/switching capacitance 10 xEV513.9nF of switching capacitance 160nF of de-coupling capacitanceEV634nF of effective switching capacitance320nF of de-coupling capacitance-not enough!,Source:B.Herrick(Compaq),EV6 De-coupling Capacitance,Design fo

25、r Idd=25 A Vdd=2.2 V,f=600 MHz0.32-F of on-chip de-coupling capacitance was addedUnder major busses and around major gridded clock driversOccupies 15-20%of die area1-F 2-cm2 Wirebond Attached Chip Capacitor(WACC)significantly increases“Near-Chip”de-coupling160 Vdd/Vss bondwire pairs on the WACC mini

26、mize inductance,Source:B.Herrick(Compaq),EV6 WACC,Source:B.Herrick(Compaq),The Transmission Line,The Wave Equation,Design Rules of Thumb,Transmission line effects should be considered when the rise or fall time of the input signal(tr,tf)is smaller than the time-of-flight of the transmission line(tfl

27、ight).tr(tf)2.5 tflightTransmission line effects should only be considered when the total resistance of the wire is limited:R 5 Z0The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance,R Z0/2,Should we be worried?,Transmissio

28、n line effects cause overshooting and non-monotonic behavior,Clock signals in 400 MHz IBM Microprocessor(measured using e-beam prober)Restle98,Matched Termination,Z,0,Z,L,Z,0,Series Source Termination,Z,0,Z,0,Z,S,Parallel Destination Termination,Segmented Matched Line Driver,Parallel TerminationTran

29、sistors as Resistors,0.5,Normalized Resistance(,V,),1,PMOS with-1V bias,NMOS-PMOS,PMOS only,NMOS only,1.5,V,R,(Volt),2,2.5,0,1.1,1,1.2,1.3,1.4,1.5,1.6,1.7,1.8,1.9,2,Out,M,r,V,dd,Out,M,r,V,dd,V,bb,Out,M,rp,M,rn,V,dd,Output Driver with Varying Terminations,V,out,(V),V,out,(V),1,2,3,4,time(sec),Revised design with matched driver impedance,V,s,V,d,V,in,5,6,7,8,0,1,0,1,2,3,4,1,2,3,4,Initial design,V,s,V,d,V,in,5,6,7,8,0,1,0,1,2,3,4,The“Network-on-a-Chip”,