嵌入式处理器架构与程式设计课件.ppt
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1、嵌入式處理器架構與程式設計,王建民中央研究院 資訊所2008年 7月,2,Contents,IntroductionComputer ArchitectureARM ArchitectureDevelopment ToolsGNU Development ToolsARM Instruction SetARM Assembly LanguageARM Assembly ProgrammingGNU ARM ToolChainInterrupts and Monitor,Lecture 10Interrupts and Monitor,4,Outline,Exception Handling a
2、nd Software InterruptsELF: Executable and Linking FormatARM Monitor and Program Loading,5,Normal Program Flow vs. Exception,Normally, programs execute sequentially (with a few branches to make life interesting) Normally, programs execute in user mode Exceptions and interrupts break the sequential fl
3、ow of a program, jumping to architecturallydefined memory locations In ARM, SoftWare Interrupt (SWI) is the “system call” exception,6,ARM Exceptions,Types of ARM exceptions Reset: when CPU reset pin is asserted undefined instruction: when CPU tries to execute an undefined op-code software interrupt:
4、 when CPU executes the SWI instruction prefetch abort: when CPU tries to execute an instruction pre-fetched from an illegal addressdata abort: when data transfer instruction tries to read or write at an illegal address IRQ: when CPUs external interrupt request pin is asserted FIQ: when CPUs external
5、 fast interrupt request pin is asserted,7,The Programmers Model,Processor Modes (of interest)User: the “normal” program execution mode.IRQ: used for general-purpose interrupt handling.Supervisor: a protected mode for the operating system.The Register SetRegisters R0-R15 + CPSRR13: Stack Pointer (by
6、convention)R14: Link Register (hardwired)R15: Program Counter where bits 0:1 are ignored (hardwired),8,Terminology,The terms exception and interrupt are often confused Exception usually refers to an internal CPU eventfloating point overflow MMU fault (e.g., page fault) trap (SWI) Interrupt usually r
7、efers to an external I/O eventI/O device request reset In the ARM architecture manuals, the two terms are mixed together,9,What do SWIs do?,SWIs (often called software traps) allow a user program to “call” the OS that is, SWIs are how system calls are implemented. When SWIs execute, the processor ch
8、anges modes (from User to Supervisor mode on the ARM) and disables interrupts.,10,SWI Example,Types of SWIs in ARM Angel (axd or armsd)SWI_WriteC(SWI 0) Write a byte to the debug channel SWI_Write0(SWI 2) Write the nullterminated string to debug channel SWI_ReadC(SWI 4) Read a byte from the debug ch
9、annel SWI_Exit(SWI 0 x11) Halt emulation this is how a program exits SWI_EnterOS(SWI 0 x16) Put the processor in supervisor mode SWI_Clock(SWI 0 x61) Return the number of centiseconds SWI_Time(SWI 0 x63) Return the number of secs since Jan. 1, 1970,11,What happens on an SWI?1,The ARM architecture de
10、fines a Vector Table indexed by exception type One SWI, CPU does the following: PC 0 x08 Also, sets LR_svc, SPSR_svc, CPSR (supervisor mode, no IRQ),12,What happens on an SWI?2,Not enough space in the table (only one instruction per entry) to hold all of the code for the SWI handler function This on
11、e instruction must transfer control to appropriate SWI Handler Several options are presented in the next slide,13,“Vectoring” Exceptions to Handlers,Option of choice: Load PC from jump table (shown below) Another option: Direct branch (limited range),14,What happens on SWI completion?,Vectoring to t
12、he S_Handler starts executing the SWI handler When the handler is done, it returns to the program at the instruction following the SWI MOVS restores the original CPSR as well as changing pc,15,How to determine the SWI number?,All SWIs go to 0 x08,16,SWI Instruction Format,Example: SWI 0 x18,17,Execu
13、ting SWI Instruction,On SWI, the processor(1) copies CPSR to SPSR_SVC (2) set the CPSR mode bits to supervisor mode (3) sets the CPSR IRQ to disable (4) stores the value (PC + 4) into LR_SVC (5) forces PC to 0 x08,LDR r0,lr,#4BIC r0,r0,#0 xff000000R0 holds SWI number,MOVS pc, lr,SWI Handler(S_Handle
14、r),18,Jump to “Service Routine”,LDR r0,lr,#4BIC r0,r0,#0 xff000000switch (r0) case 0 x00: service_SWI1(); case 0 x01: service_SWI2(); case 0 x02: service_SWI3();,MOVS pc, lr,SWI Handler(S_Handler),On SWI, the processor(1) copies CPSR to SPSR_SVC (2) set the CPSR mode bits to supervisor mode (3) sets
15、 the CPSR IRQ to disable (4) stores the value (PC + 4) into LR_SVC (5) forces PC to 0 x08,19,Problem with The Current Handler,On SWI, the processor(1) copies CPSR to SPSR_SVC (2) set the CPSR mode bits to supervisor mode (3) sets the CPSR IRQ to disable (4) stores the value (PC + 4) into LR_SVC (5)
16、forces PC to 0 x08,LDR r0,lr,#4BIC r0,r0,#0 xff000000switch (r0) case 0 x00: service_SWI1(); case 0 x01: service_SWI2(); case 0 x02: service_SWI3();,MOVS pc, lr,SWI Handler(S_Handler),What was in R0? User program may have been using this register. Therefore, cannot just use it must first save it,20,
17、Full SWI Handler,S_Handler:SUB sp, sp, #4 leave room on stack for SPSR STMFD sp!, r0r12, lr store users gp registersMRS r2, spsr get SPSR into gp registersSTR r2, sp, #14*4 store SPSR above gp registersMOV r1, sp pointer to parameters on stack LDR r0, lr, #4 extract the SWI number BIC r0,r0,#0 xff00
18、0000 get SWI # by bit-maskingBL C_SWI_handler go to handler (see next slide) LDR r2, sp, #14*4 restore SPSR (NOT “sp!”)MSR spsr_csxf, r2 csxf flagsLDMFD sp!, r0r12, lr unstack users registers ADD sp, sp, #4 remove space used to store SPSR MOVS pc, lr return from handler,gp = general-purpose,SPSR is
19、stored above gp registers since the registers may contain system call parameters (sp in r1),21,C_SWI_Handler,void C_SWI_handler(unsigned number, unsigned *regs) switch (number) case 0: /* SWI number 0 code */ break; case 1: /* SWI number 1 code */ break; . case 0 x100: puts(“SWI 0 x100 trigged!n”);
20、break;. case XXX: /* SWI number XXX code */ break; default: /* end switch */ /* end C_SWI_handler() */,22,Loading the Vector Table,/* For 18-349, the Vector Table will use the LDR PC, PC, * offset springboard approach */unsigned Install_Handler(unsigned int routine, unsigned int *vector) unsigned in
21、t pcload_instr, old_handler, *soft_vector; pcload_instr = *vector; /* read the Vector Table instr (LDR .) */ pcload_instr ,23,.text .align 2 .global triggertrigger: STMFD sp!, lr SWI #0 x100 LDMFD sp!, pc,extern void S_Handler();extern void trigger();int main() unsigned *swivec = (unsigned *) 0 x08;
22、 unsigned backup; backup = Install_Handler (unsigned) S_Handler, swivec); trigger(); Install_Handler (backup, swivec);,Example: SWI Application,24,Exercise #3,Write a service routine that receives a file name from a trigger and display the first lines of the file on the screen.Void service101(char *
23、filename);Write a trigger that pass a file name as an argument to the above service routine through SWI #0 x101.void trigger101(char *filename);Write a main program to perform a demonstration.,25,Outline,Exception Handling and Software InterruptsELF: Executable and Linking FormatARM Monitor and Prog
24、ram Loading,26,Introduction to ELF,Executable and Linking FormatDeveloped by Unix System Lab.Default binary format on Linux, Solaris 2.x, etcSome of the capabilities of ELF are dynamic linking, dynamic loading, imposing runtime control on a program, and an improved method for creating shared librari
25、es.The ELF representation of control data in an object file is platform independent.,27,Three Types of ELF Files,Relocatable filedescribes how it should be linked with other object files to create an executable file or shared library.Executable filesupplies information necessary for the operating sy
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