化学气相沉积概况课件.ppt

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1、Chapter 10CVD and Dielectric Thin Film,2022/11/7,1,Chapter 10CVD and Dielectric,CVD Oxide vs. Grown Oxide,Grown film,Deposited film,Bare silicon,SiO2,SiO2,Si,Si,Si,2022/11/7,2,CVD Oxide vs. Grown OxideGrown,CVD Oxide vs. Grown Oxide,GrowOxygen is from gas phaseSilicon from substrateOxide grow into s

2、iliconHigher quality,CVDBoth oxygen and silicon are from gas phaseDeposit on substrate surfaceLower temperatureHigher growth rate,2022/11/7,3,CVD Oxide vs. Grown OxideGrowC,Dielectric Thin Film Applications,As a dielectric layer in multilevel metal interconnectionShallow trench isolation (STI) betwe

3、en transistorsSidewall spacer for salicide, LDD, and the source/drain diffusion bufferThe passivation dielectric (PD) Dielectric ARC for feature size 0.25 mm,2022/11/7,4,Dielectric Thin Film Applicati,Dielectric Thin Film Applications,Inter layer dielectric, or ILD, include PMD and IMDPre-metal diel

4、ectric: PMDnormally PSG or BPSGTemperature limited by thermal budgetInter-metal dielectric: IMDUSGNormally deposited around 400 C,2022/11/7,5,Dielectric Thin Film Applicati,Oxide,Nitride,USG,W,P-wafer,N-well,P-well,BPSG,p,+,p,+,n,+,n,+,USG,W,Metal 2, AlCu,P-epi,Metal 1, AlCu,AlCu,STI,Figure 10.2,STI

5、,PMD or ILD1,IMD or ILD2,ARC,PD1,PD2,Sidewall spacer,WCVD,TiN CVD,2022/11/7,6,OxideNitrideUSGWP-waferN-wellP,Dielectric Processes,An N-layer metal interconnection IC chip with STI, the minimum number of dielectric process is:,Dielectric layer =,1,+ 1,+ 1,+ (N-1),+ 1 = N + 3,STI,spacer,PMD IMD,PD,202

6、2/11/7,7,Dielectric ProcessesAn N-layer,CVD,Chemical Vapor DepositionChemical gases or vapors react on the surface of solid, produce solid byproduct on the surface in the form of thin film. Other byproducts are volatile and leave the surface.,2022/11/7,8,CVDChemical Vapor Deposition20,CVD Applicatio

7、ns,2022/11/7,9,CVD Applications2022/10/109,CVD,Gas or vapor phase precursors are introduced into the reactor Precursors across the boundary layer and reach the surfacePrecursors adsorb on the substrate surfaceAdsorbed precursors migrate on the substrate surfaceChemical reaction on the substrate surf

8、aceSolid byproducts form nuclei on the substrate surfaceNuclei grow into islandsIslands merge into the continuous thin filmOther gaseous byproducts desorb from the substrate surfaceGaseous byproducts diffuse across the boundary layerGaseous byproducts flow out of the reactor.,2022/11/7,10,CVDGas or

9、vapor phase precurso,Figure 10.3,Reactants,Byproducts,Showerhead,Pedestal,Wafer,Precursors,Forced,convection,region,Boundary,layer,2022/11/7,11,Figure 10.3ReactantsByproducts,Deposition Process,Precursor arrives surface,Migrate on the surface,React on the surface,Nucleation: Island formation,2022/11

10、/7,12,Deposition ProcessPrecursor ar,Deposition Process,Islands grow,Islands grow, cross-section,Islands merge,Continuous thin film,2022/11/7,13,Deposition ProcessIslands grow,CVD Processes,APCVDLPCVDPECVD,2022/11/7,14,CVD ProcessesAPCVD2022/10/1014,Atmospheric Pressure CVD,CVD process taking place

11、at atmospheric pressureAPCVD process has been used to deposit silicon oxide and silicon nitrideAPCVD O3-TEOS oxide process is widely used in the semiconductor industry, especially in STI and PMD applicationsConveyor belt system with in-situ belt clean,2022/11/7,15,Atmospheric Pressure CVDCVD pr,Heat

12、er,Wafers,N2,N2,Process Gas,Exhaust,Wafers,Conveyor Belt,Belt Clean Station,APCVD Reactor,2022/11/7,16,HeaterWafersN2N2Process GasExh,Question,A semiconductor manufacturer has its R&D lab on the coast near sea level and one of its manufacturing fabs on a high altitude plateau. It was found that the

13、APCVD processes developed in the R&D lab couldnt directly apply in that particular fab. Why?,2022/11/7,17,QuestionA semiconductor manufa,Answer,On a high-altitude plateau, the atmospheric pressure is significantly lower than at sea level. Because earlier APCVD reactor didnt have a pressure-control s

14、ystem, a process that worked fine in the R&D lab at sea level might not work well in the high altitude fab because of pressure difference,2022/11/7,18,AnswerOn a high-altitude plate,LPCVD,Longer MFPGood step coverage & uniformityVertical loading of wafer Fewer particles and increased productivityLes

15、s dependence on gas flowVertical and horizontal furnace,2022/11/7,19,LPCVDLonger MFP2022/10/1019,Horizontal Conduction-Convection-heated LPCVD,Adaptation of horizontal tube furnaceLow pressure: from 0.1 to 1 TorrUsed mainly for polysilicon, silicon dioxide and silicon nitride filmsCan process 200 wa

16、fers per batch,2022/11/7,20,Horizontal Conduction-Convecti,LPCVD System,Heating Coils,Quartz Tube,To Pump,Pressure Sensor,Process Gas Inlet,Loading Door,Wafers,Center ZoneFlat Zone,Distance,Temperature,Wafer Boat,2022/11/7,21,LPCVD SystemHeating CoilsQuart,PECVD,Developed when silicon nitride replac

17、ed silicon dioxide for passivation layer.High deposition rate at relatively low temp.RF induces plasma field in deposition gasStress control by RFChamber plasma clean.,2022/11/7,22,PECVDDeveloped when silicon ni,Plasma Enhanced CVD System,Process gases,Process chamber,By-products to the pump,Heated

18、plate,Wafer,Plasma,RF power,2022/11/7,23,Plasma Enhanced CVD SystemProc,Step Coverage,A measurement of the deposited film reproducing the slope of a step on the substrate surfaceOne of the most important specifications Sidewall step coverageBottom step coverageConformalityOverhang,2022/11/7,24,Step

19、CoverageA measurement of,Step Coverage and Conformity,a,b,c,d,Substrate,Structure,CVD thin film,Sidewall step coverage = b/a Bottom step coverage = d/aConformity = b/c Overhang = (c - b)/bAspect ratio = h/w,h,w,2022/11/7,25,Step Coverage and Conformityab,Factors Affect Step Coverage,Arriving angle o

20、f precursor Surface mobility of adsorbed precursor,2022/11/7,26,Factors Affect Step CoverageAr,Arriving Angles,A,B,C,270,90,180,2022/11/7,27,Arriving AnglesABC270901802,Arriving Angle,Corner A: 270, corner C: 90 More precursors at corner A More depositionForm the overhangOverhang can cause voids or

21、keyholes,2022/11/7,28,Arriving AngleCorner A: 270,Void Formation Process,Metal,Dielectric,Dielectric,Dielectric,Void,Metal,Metal,2022/11/7,29,Void Formation ProcessMetal Di,Control of Arriving Angle,Changing pressureTapering opening,2022/11/7,30,Control of Arriving AngleChang,Step Coverage, Pressure

22、 and Surface Mobility,APCVD No mobility,LPCVD No mobility,High mobility,2022/11/7,31,Step Coverage, Pressure and Su,Silicon,PSG,Nitride,Larger arriving angle,Smaller arriving angle,Arriving Angles, Contact Holes,2022/11/7,32,SiliconPSGNitrideLarger arrivi,Gap Fill,Fill a gap without voids Voids: cau

23、se defect and reliability problemsDeposition/Etchback/DepositionConformal depositionO3-TEOS and tungsten CVDHigh density plasma CVD,2022/11/7,33,Gap FillFill a gap without voi,Gap Fill,PMD: zero tolerance voids Tungsten can be deposited into these voids Causing shortsIMD: voids below metal may toler

24、ablereducing kprocess gas could come out later and cause reliability problem,2022/11/7,34,Gap FillPMD: zero tolerance vo,Void in PMD,Silicide,Void,Silicide,Top view,Before W CVD,Contact,Sidewall spacers,2022/11/7,35,Void in PMDSilicideVoidSilicid,Unwanted W Line Between Gates,Silicide,Tungsten,Silic

25、ide,Top view,After W CVD,W plug,Sidewall spacers,2022/11/7,36,Unwanted W Line Between GatesS,Deposition/Etchback/Deposition,AlCu,AlCu,AlCu,USG,USG,USG,Dep.,Dep.,Etch,2022/11/7,37,Deposition/Etchback/Deposition,Conformal Deposition Gap Fill,2022/11/7,38,Conformal Deposition Gap Fill2,Conformal Deposi

26、tion Gap Fill,2022/11/7,39,Conformal Deposition Gap Fill2,Conformal Deposition Gap Fill,2022/11/7,40,Conformal Deposition Gap Fill2,Metal,Metal,Metal,Metal,Metal,Metal,Metal,Metal,Metal,HDP CVD Gap Fill,2022/11/7,41,MetalMetalMetalMetalMetalMetal,Surface Adsorption,Determine precursors surface mobil

27、ity Affect step coverage and gap fillPhysical adsorption (physisorption)Chemical adsorption (chemisorption),2022/11/7,42,Surface AdsorptionDetermine pr,Chemisorption,Actual chemical bonds between surface atom and the adsorbed precursor moleculeBonding energy usually exceeding 2 eVLow surface mobilit

28、yIon bombardment with10 to 20 eV energy in PECVD processes can cause some surface migration of chemisorbed precursors,2022/11/7,43,ChemisorptionActual chemical b,Physisorption,Weak bond between surface and precursorBonding energy usually less than 0.5 eV Hydrogen bondingVan der Waals forces Ion bomb

29、ardment and thermal energy at 400 C can cause migration of physisorbed precursorsHigh surface mobility,2022/11/7,44,PhysisorptionWeak bond between,Distance from surface,Bonding energy,Substrate Surface,Chemisorbed precursor,Physisorbed precursor,Adsorptions,2022/11/7,45,Distance from surface Bonding

30、,Dielectric CVD Precursors,Silane (SiH4) TEOS (tetra-ethyl-oxy-silane, Si(OC2H5)4),2022/11/7,46,Dielectric CVD PrecursorsSilan,CVD Precursor: Silane,Dielectric CVDPECVD passivation dielectric depositionsPMD barrier nitride layer Dielectric anti reflective coating (DARC)High density plasma CVD oxide

31、processes LPCVD poly-Si and silicon nitrideMetal CVDW CVD process for nucleation step Silicon source for WSix deposition,2022/11/7,47,CVD Precursor: SilaneDielectri,Dielectric CVD Precursor: Silane,Pyrophoric (ignite itself), explosive, and toxicOpen silane line without thoroughly purging can cause

32、fire or minor explosion and dust line,2022/11/7,48,Dielectric CVD Precursor: Sila,H,Si,H,H,H,Structure of Silane Molecule,Si,H,H,H,H,2022/11/7,49,HSiHHHStructure of Silane Mole,CVD Precursor Adsorption: Silane,Silane molecule is perfectly symmetrical Neither chemisorb nor physisorb Fragments of sila

33、ne, SiH3, SiH2, or SiH, can easily form chemical bonds with surface Low surface mobility, overhangs and poor step coverage,2022/11/7,50,CVD Precursor Adsorption: Sila,CVD Precursor Adsorption: TEOS,TEOS (tetra-ethyl-oxy-silane, Si(OC2H5)4)Big organic molecule TEOS molecule is not perfectly symmetric

34、 Can form hydrogen bond and physisorb High surface mobilityGood step coverage, conformality, and gap fillWidely used for oxide deposition,2022/11/7,51,CVD Precursor Adsorption: TEOS,Si,H,H,H,H,H,H,H,H,C,C,O,O,H,H,H,H,C,C,C,C,O,C,C,O,H,H,H,H,H,H,H,H,TEOS Molecule,2022/11/7,52,SiHHHHHHHHCCOOHHHHCCCCOC

35、COHHHH,TEOS Applications,STI, sidewall spacer, PMD, and IMDMost dielectric CVD processes are TEOS based oxide processes,2022/11/7,53,TEOS Applications STI, sidewal,1,3,10,30,100,10,20,30,40,50,60,70,80,90,100,110,Vapor Pressure (Torr),Temperature (C),TEOS Vapor Pressure,1,3,10,30,100,2022/11/7,54,13

36、1030100102030405060708090100,TEOS Delivery,A liquid at room temperature with boiling point at the sea level is 168 CAs a reference, boiling point of water (H2O) at sea level is 100 CNeed delivery system to send its vapor to process chamberBoiler, bubbler, and injection systems,2022/11/7,55,TEOS Deli

37、very A liquid at room,MFC,Process chamber,Pump,TEOS,Thermostatic oven,Heated gas line,Heated foreline,Boiler System,2022/11/7,56,MFCProcess chamberPumpTEOSTher,Liquid TEOS,Thermostatic oven,MFC,MFM,Process chamber,Pump,Carrier gas,Carrier gas bubbles,Heated gas line,Bubbler System,2022/11/7,57,Liqui

38、d TEOSThermostatic ovenMF,LFC,Process chamber,Pump,MFC,Carrier gas,Injection valve,Liquid TEOS,Pressurize gas,Liquid TEOS flow,Heated gas line, TEOS vapor and carrier gas,Injection System,2022/11/7,58,LFCProcess chamberPumpMFCCarri,Sticking Coefficient,The probability that precursor atom forms chemi

39、cal bond with surface atom in one collision Can be calculated by comparing the calculated deposition rate with 100% sticking coefficient and the measured actual deposition rate,2022/11/7,59,Sticking CoefficientThe probab,Sticking Coefficient,Precursors,Sticking Coefficient,SiH,4,3,10,-4,to 3,10,-5,S

40、iH,3,0.04 to 0.08,SiH,2,0.15,SiH,0.94,TEOS,10,-3,WF,6,10,-4,2022/11/7,60,Sticking CoefficientPrecursors,Step Coverage of TEOS and Silane Oxide,TEOS,Silane,2022/11/7,61,Step Coverage of TEOS and Sila,Question,Why dont people apply TEOS as the silicon source gas for the silicon nitride deposition to g

41、et better step coverage for the nitride film,2022/11/7,62,QuestionWhy dont people apply,Answer,In the TEOS molecule, the silicon atom is bonded with four oxygen atoms. It is almost impossible to strip all oxygen atoms and have silicon bonded only with nitrogen. Therefore, TEOS is mainly used for the

42、 oxide deposition and the nitride deposition normally uses silane as the silicon source gas,2022/11/7,63,AnswerIn the TEOS molecule, th,Chemical Reaction Rate,2022/11/7,64,Chemical Reaction Rate2022/10/,Deposition Regimes,1/,T,ln,D.R,.,Mass-transport-limited,regime,Surface-reaction-,limited regime,S

43、lope = -E,a,/k,Gas-phase-nucleation,regime,2022/11/7,65,Deposition Regimes 1/Tln D.R.M,Surface-Reaction-Limited Regime,Chemical reaction rate cant match precursor diffusion and adsorption rates; precursors pile up on the substrate surface and wait their turn to react. D.R. = C.R. B C Deposition rate

44、 is very sensitive to temperature,2022/11/7,66,Surface-Reaction-Limited Regim,Mass-Transport-Limited Regime,When the surface chemical reaction rate is high enough, the chemical precursors react immediately when they adsorb on the substrate surface. Deposition rate = D dn/dx B C Deposition rate is in

45、sensitive to temperature Mainly controlled by gas flow rates,2022/11/7,67,Mass-Transport-Limited RegimeW,Temperature,Deposition rate,Dep. rate,insensitive to,temperature,Dep. rate,sensitive to,temperature,Deposition Rage Regimes,2022/11/7,68,TemperatureDeposition rateDep,CVD Reactor Deposition Regim

46、e,Most single wafer process reactors are designed in mass-transport-limited regimeIt is easier to control the gas flow rate Plasma or unstable chemicals such as ozone are used to achieve mass-transport-limited-regime at relatively low temperature,2022/11/7,69,CVD Reactor Deposition RegimeM,Applicati

47、ons of Dielectric Thin film,Shallow trench isolation (STI, USG)Sidewall Spacer (USG)Pre-metal dielectric (PMD, PSG or BPSG)Inter-metal dielectric (IMD, USG or FSG)Anti-reflection coating (ARC, SiON)Passivation dielectric (PD, Oxide/Nitride),2022/11/7,70,Applications of Dielectric Thi,Dielectric CVD,

48、 Oxide and Nitride,Oxide (SiO,2,),Nitride (Si,3,N,4,),Similar dielectric strength, 1,10,7,V/cm,Similar dielectric strength, 1,10,7,V/cm,Lower dielectric constant,k,= 3.9,Higher dielectric constant,k,= 7.0,Not a good barrier for moisture and,mobile ion (,Na,+,),Good barrier for moisture and mobile io

49、n,(,Na,+,),Transparent to UV,Conventional nitride opaque to UV,Can be doped with P and B,2022/11/7,71,Dielectric CVD, Oxide and Nitr,Shallow Trench Isolation (STI),Grow pad oxide Deposition nitride,Etch nitride, oxide and silicon,Grow barrier oxide CVD USG trench fill,CMP USGAnneal USG,Si,Si,Si,Si,S

50、i,Strip nitride and oxide,USG,USG,USG,2022/11/7,72,Shallow Trench Isolation (STI),Shallow Trench Isolation (STI),2022/11/7,73,Shallow Trench Isolation (STI),Sidewall Spacer Formation,Lightly doped drain (LDD)Self aligned silicide (Salicide),2022/11/7,74,Sidewall Spacer FormationLight,PMD,Doped oxide