SoC设计与验证课件.ppt

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1、SoC设计与验证,实验一 RTL设计,1,SoC设计与验证实验一 RTL设计1,本课程的学习内容,SoC设计方法：基于IP的方法SoC的设计实现（自顶向下）：软件实现，硬件实现（逻辑仿真、逻辑综合、物理设计）物理设计：由于时间的关系，作为选做内容下面的内容，结合项目设计实验进一步学习和实践基于IP的设计方法和自顶向下的设计实现方法,2,本课程的学习内容SoC设计方法：基于IP的方法2,Turbo Eagle SoC,体系结构IP模块CPUDSP外围接口存储器BUS软件,3,Turbo Eagle SoC体系结构3,第三讲 内容,RTL级设计TE的RTL设计,4,第三讲 内容RTL级设计4,RT

2、L设计,Register Transition Level寄存器传输级设计是一种硬件结构形式RTL设计中数据来自寄存器，计算完成后的结果存入寄存器，即设计以寄存器为边界构建寄存器：多位的时序逻辑（触发器和锁存器），用于存储电路状态,5,RTL设计Register Transition Level,RTL：行为和结构混合设计,Design Iteration,6,RTL：行为和结构混合设计HDLLogic Synthesi,RTL设计有限状态机,设计以寄存器为边界构建,7,RTL设计有限状态机设计以寄存器为边界构建7,RTL设计流水线结构,Reference,Pipelined,8,RTL设计流

3、水线结构ReferencePipelined,时序逻辑：register,Latch电平敏感,D,Clk,Q,D,Clk,Q,Flip Flop时钟沿敏感,Clk,Clk,D,D,Q,Q,9,时序逻辑：registerLatchDClkQDClkQFl,基于锁存器和触发器的设计,在一个时钟周期内，组合逻辑完成一次计算，把计算结果存到时序逻辑中,10,基于锁存器和触发器的设计在一个时钟周期内，组合逻辑完成一次计,RTL级设计设计输入,利用硬件描述语言可以对RTL级的设计进行设计输入Verilog中一般利用过程结构（initial，always），引入寄存器，构建RTL级设计逻辑综合器可以对RTL

4、级HDL进行优化实现,11,RTL级设计设计输入利用硬件描述语言可以对RTL级的设计,RTL级设计逻辑综合,逻辑综合器可以将RTL级的HDL转换为寄存器和组合逻辑结构，并映射到具体的工艺库逻辑综合器是自顶向下设计流程中最关键的EDA工具之一,12,RTL级设计逻辑综合逻辑综合器可以将RTL级的HDL转换,自顶向下的设计方法,逻辑综合器使得自顶向下的设计方法成为可能ASIC和SoC的设计方法取代全定制方法，成为数字VLSI的主流方法ASIC是基于标准单元的方法，而SoC是基于IP的方法,13,自顶向下的设计方法逻辑综合器使得自顶向下的设计方法成为可能1,第三讲 内容,RTL级设计TE的RTL设计

5、,14,第三讲 内容RTL级设计14,实验目的,掌握基于IP集成的SoC的设计方法进一步熟悉和掌握利用cadence工具进行自顶向下的设计实现的过程完成IP集成、逻辑仿真以及逻辑综合过程,15,实验目的掌握基于IP集成的SoC的设计方法15,实验内容,在现有的Turbo Eagle设计的基础上，增加一个IP软核PCI bridge，实现系统对外部PCB板上的PCI总线接口的支持RTL设计：增加PCI软核软件设计：增加PCI软核需要的软件，并编译实现逻辑仿真：PCI单元仿真和全系统仿真设计实现：对新的TE进行逻辑综合和物理设计,16,实验内容在现有的Turbo Eagle设计的基础上，增加一个,

6、时间安排（第二周第八周）,第二周第三周：IP集成方法（包括PCI IP核的RTL设计）第四周第五周：包括PCI IP的Turbo Eagle的逻辑仿真第六周第七周：逻辑综合和门级仿真第八周：项目检查,17,时间安排（第二周第八周）第二周第三周：IP集成方法（,实验要求,设计内容：完成软核的集成、软件设计和实现、逻辑仿真和逻辑综合的内容，物理设计为选做内容设计报告：提交设计报告考察方式：设计数据和设计报告各占据期末成绩的50参考文件：570/starter_kit/slides/下的文件,18,实验要求设计内容：完成软核的集成、软件设计和实现、逻辑仿真和,实验：第一部分,PCI软核的逻辑设计与集

7、成PCI总线IPRTL设计软件设计,19,实验：第一部分PCI软核的逻辑设计与集成19,PCI软核的逻辑设计与集成,PCI软核The PCI-Bridge HDL code软核的RTL描述文件A full standalone testbench ready for simulationExample C firmware for the Leon to program the PCI-Bridge提供给我们软核（在starter kit目录下），我们要利用软核实现IP集成，包括硬件集成和软件实现并对集成后的系统进行验证和实现,20,PCI软核的逻辑设计与集成PCI软核20,项目设计：RTL设

8、计,PCI总线的工作原理PCI总线IP的结构PCI总线IP的仿真验证IP集成软件实现（不作要求）,21,项目设计：RTL设计PCI总线的工作原理21,PCI总线的工作原理,参考”PCI local bus specification”PCI总线的spec总线的信号总线的工作,22,PCI总线的工作原理参考”PCI local bus spe,The PCI Bus,PCI Special Interest Group: Developed in 1993 for Intel Personal ComputersPCB板上的总线，在PC中连接各种外围设备,23,The PCI BusPCI Sp

9、ecial Interes,The PCI Bus：Specifications,Synchronous 33 MHz transfers, 33MHz x 4byte = 132Mb/sec32 Multiplexed Address/Data Lines (saves pins and cost)Basic Transfers: 1) Address Phase, 2) Data PhaseCPU Architecture independent (also used by Sun, Apple etc.)Supports Plug&Play with Configuration Regi

10、sters/Cycles,24,The PCI Bus：SpecificationsSync,The PCI Bus：Specifications,Bus Master: “PCI Initiator”, Bus Slave: “PCI Target”Burst Data Phases continue until Initiator deasserts Frame#66MHz, 64 bit Versions availableSupports 5V and 3.3V operationBus Signal Integrity guaranteed with special PCI-IO p

11、ads (slew limited)Only 4 Slots allowed, Extensions only with PCI-to-PCI Bridge,25,The PCI Bus：SpecificationsBus,PCI总线的工作原理,参考”PCI local bus specification”PCI总线的spec总线的信号总线的工作,26,PCI总线的工作原理参考”PCI local bus spe,PCI 总线信号,System SignalsClk: 33MHz or 66Mhz, Data synchronized to rising edgeRST#: Asynchron

12、ous Reset, asserted for 100usec,27,PCI 总线信号System Signals27,PCI 总线信号,Data SignalsAD31:0Multiplexed 32-bit Address/Data BusAddress Phase: Following High-Low transistion on “Frame#”Data Phase: IRDY# and TRDY# must be low to complete transferBurst transfer: Data Phase lasts several cycles, Frame# goes

13、High in last cycleC/BE#3:0Address Phase: Indicates the type of transferData Phase: Indicates which bytes are valid (Byte-Enable)Par: Used to implement Even Parity,28,PCI 总线信号Data Signals28,PCI总线信号：Control Signals,Frame#: Indicate Address/Data Phase, End of TransferIRDY#: Initiator ReadyTRDY#: Target

14、 ReadyStop#: Used by Target to cancel/suspend a transferLock#: For Initiator to get exlusive access to a TargetDEVSEL#: Target indication that it was selectedIDSEL: Unique for each slot, indicates Configuration CyclePCI Initiator Arbitration SignalsREQ#: Unique for each slot, Requests the BusGNT#: U

15、nique for each slot, Grants the BusSlot-unique signals: System Arbiter can choose arbitration algorithm,29,PCI总线信号：Control SignalsFrame#:,PCI总线的工作原理,参考”PCI local bus specification”PCI总线的spec总线的信号总线的工作,30,PCI总线的工作原理参考”PCI local bus spe,PCI Configuration Cycles,PCI Supports Plug&Play，插上PCI器件以后，系统启动过程中

16、会自动检查，并为该器件分配地址空间PCI Bridge作为amba总线上的一个器件，有固定的地址，在本设计中将占据DES的地址PCI Bridge需要为PCB板上挂在PCI总线上的器件分配地址为了支持即插即用，PCI总线协议中包括配置周期，来让host对PCI器件进行地址分配,31,PCI Configuration CyclesPCI Su,PCI Configuration Cycles,在配置周期中，PCI总线对总线上的器件进行配置，即根据需要分配地址这不同于一般的IO和存储器的寻址方式，一般来说，总线上的器件都被给定一段地址，就像PCI Bridge在amba总线上一样PCI-Brid

17、ge负责启动PCI总线的配置周期配置周期也分为读写操作，host从器件读取器件名称和ID等信息，并把基址base address写到器件中的寄存器中，根据器件的需要分配其一段地址空间,32,PCI Configuration Cycles在配置周期中,PCI Configuration Cycles,How to address a device before it has an address?The PCI Configuration Read and Write CyclesEach slot has an IDSEL lineThat line is asserted, and AD0

18、:1 is 00AD7:2 provides the address of the configuration registerC/BE3:0 specifies “Configuration Read” or “Configuration Write”,33,PCI Configuration CyclesHow to,PCI总线的工作时序,从地址周期开始，然后进入数据周期数据传输期间FRAME信号有效IRDY和TRDY都有效期间传输数据DEVSEL信号通知总线，该目标器件正在被读写,34,PCI总线的工作时序从地址周期开始，然后进入数据周期34,项目设计：RTL设计,PCI总线的工作原理P

19、CI总线IP（pci_bridge）的结构PCI总线IP的仿真验证IP集成软件实现（不作要求）,35,项目设计：RTL设计PCI总线的工作原理35,The Goal: Bring in the PCI Bus,PCI Bridge,WishboneSlave,WishboneMaster,PCIInitiator,PCITarget,PCIArbiter,PCITarget,AmbaWishboneWrapper,Amba Bus,Turbo Eagle,Testbench,The PCI-Bridge has 2-directional data flowFrom the PCI Bus t

20、o the PCI-Target to the Wishbone MasterFrom the Amba Bus to the Wishbone Slave to the PCI InitiatorFor this project we only use the outbound directionReceived PCI data is stored in “PCI_OUTPUT”, compare to Golden File,PCI_OUTPUT,PCI Bus,36,The Goal: Bring in the PCI Bus,PCI总线器件寻址的实现,Bridge采用image的方法

21、来实现对PCI器件的寻址和配置对于wishbone slave方式来说，bridge中包括最多5个image来表示可能的PCI器件来自amba（wishbone）总线的地址被映射到某个image上，经过地址转换寻址该image所表示的PCI总线上的器件,37,PCI总线器件寻址的实现Bridge采用image的方法来实,PCI-Bridge Operation,The PCI-Bridge can have up to 5 ImagesImage 0 is mandatory, provides Register accessThis project uses Image 0 and Imag

22、e 1Image 1 is configured at run-time,Amba Bus,Image 0,Image 1,Image 2,Image 3,Image 4,Bus Address,=,Image 1-4:Address Translation,PCI Bus,Image 0:AccessPCI-BridgeRegisters,Matchesany Image?,PCI-Bridge,38,PCI-Bridge OperationThe PCI-Br,The Imaging Mechanism,Image translation is necessaryThe PCI side

23、memory map is known only at runtimeCannot hope that the Amba memory map matches the PCI sideEach Implemented Image has 4 RegistersBase AddressAddress MaskTranslation RegisterControl Register,39,The Imaging MechanismImage tra,The Imaging Mechanism,Each Implemented Image has 4 RegistersFor every imcom

24、ing address on the Amba busChecks if it fits the Base address of Image1 through Image4Checks the control register if translation is enabledIf yes, bits specified in Mask are replaced by those in TranslationThis is the address that is output to the PCI Bus,40,The Imaging MechanismEach Impl,Translatio

25、n in the Turbo-Eagle,The PCI-Bridge replaces an other block on the AMBA busMemory address range: $A012 0000 $A013 FFFF,41,Translation in the Turbo-Eagle,Translation in the Turbo-Eagle,At the minimum 2 Images are neededImage 0: To access the internal PCI-Bridge RegistersThis is the only image with a

26、hardcoded Base addressBecause this address does not change even at runtimeFor the Turbo Eagle: Choose $A012 0000Image 1: To access the PCI-BusBase Address set to A013 0000 No address translationImage 1 is programed by the Leon in the Firmware,42,Translation in the Turbo-Eagle,Guest or Host Implement

27、ation,For every bridge there are 2 fundamental modesThe main CPU sits on the Amba sideThe main CPU sits on the PCI sideTherefore, there are 2 implementation modes“Host” (acts as a Bus Master on behalf of the Amba-bus CPU)“Guest” (acts as a Slave to the CPU on the PCI Bus),43,Guest or Host Implementa

28、tionFo,Guest or Host Implementation,“Host” (acts as a Bus Master on behalf of the Amba-bus CPU)“Guest” (acts as a Slave to the CPU on the PCI Bus)Biggest difference: Access to the PCI-Bridge internal registers“Host”: From the Amba bus, which is where the main CPU is“Guest”: From the PCU, which is wh

29、ere the main CPU isFor the Turbo-Eagle: Select “Host” implementation,44,Guest or Host Implementation“H,The PCI-Bridge RTL Code,在starter_kit/pci_bridge/rtl目录下No RTL code modifications necessaryTo verify the Image 0 Base Address:pci_user_constants.v Line 218To add more Images (Image 2, 3 and 4)pci_use

30、r_constants.v Lines 201-204To verify that we are doing a “Host” implementationpci_user_constants.v Line 130Toplevel Module“pci_bridge32” in pci_bridge32.v,45,The PCI-Bridge RTL Code在starte,The PCI-Bridge RTL Code,Toplevel Module“pci_bridge32” in pci_bridge32.vThere is also a “top.v”Not used, not nee

31、dedIllustrates how to place the toplevel module into a padframeBut uses “bufif” statements instead of real pads,46,The PCI-Bridge RTL CodeTopleve,项目设计：RTL设计,PCI软核的介绍PCI总线IP的结构PCI总线IP的仿真验证IP集成软件实现,47,项目设计：RTL设计PCI软核的介绍47,设计过程,开始进行IP集成之前，先验证一下提供的IP软核的功能是否正确利用提供的testbench单独对IP进行逻辑仿真在pci_bridge目录中进行IP的仿

32、真验证仿真的命令写成了shell脚本文件run_pci命令中启动仿真器Testbench和RTL设计 在compile.f文件中指示路径,48,设计过程开始进行IP集成之前，先验证一下提供的IP软核的功能,Running the Simulation,To run the standalone simulationcd starter_kit/pci_bridgerun_pcidiff PCI_OUTPUT PCI_OUTPUT.goldThe script “run_pci” both compiles and simulates the RTLNo output from the “dif

33、f” command: “Simulation successful”,49,Running the SimulationTo run t,The PCI-Bridge Testbench,The testbench simulatesA Wishbone MasterA PCI bus, complete with Arbiter and TargetNothing is connected to the PCI-Bridge Wishbone Master PortThe testbench toplevel is in ./testbench/system.vData is sent f

34、rom the Wishbone side through the PCI Bridge to the PCI TargetAll received data is written to PCI_OUTPUT,pci_brige32.vDUT“pci_bridge32”,pci_side.vSimulates aPCI Arbiter andPCI Target Device,wb_side.vSimulates aWishbone Master,PCI_OUTPUT,Wishbone Slave,Wishbone Master,PCI,50,The PCI-Bridge TestbenchT

35、he te,Running the Simulation,The script “run_pci” both compiles and simulates the RTLThe Big PictureThe code of “pci_side.v” will be part of the Turbo-Eagle testbenchThe functionality of “wb_side.v” will go into Leon Firmware“pci_bridge32” will be instantiated in the Turbo-Eagle coreThe Wishbone sid

36、eInitializes the registers and Image 1 in the PCI BridgeInitializes the PCI Target with a Configuration WriteSends the jpeg data that later the Leon will also sendThis means the Golden File here is the same as for the final simulation,51,Running the SimulationThe scri,Sequence of Testbench Events,Th

37、e simulation is controlled by “wb_side.v”The starting point is the “initial” at line 79There are 2 main tasksinit_PCI_BridgeConfigure the PCI-Target in the PCI-BridgeBrowse the PCI Bus for PCI DevicesInitialize control registers in the PCI-BridgeInitialize Image-1 in the PCI-BridgeInitialize the PCI

38、-Target device on the PCI-Bussend_jpeg_dataSends 146 words of data to the PCI-Target deviceThis is the same data as will be sent later by the Leon,52,Sequence of Testbench EventsTh,项目设计：RTL设计,PCI软核的介绍PCI总线的工作原理PCI总线IP的仿真验证IP集成软件实现（不作要求）,53,项目设计：RTL设计PCI软核的介绍53,IP集成的过程,Add RTL source codeCompile RTL

39、source codeModify Turbo Eagle core and toplevelAdd Firmware source codeCompile firmwareAdd Testbench codeRun RTL Simulation,54,IP集成的过程Add RTL source code54,IP集成：RTL设计过程,如何开始IP集成利用提供的PCI Bridge RTL 代码在TE顶层结构中例化该IP，并进行连接在padframe文件中为该IP增加相应的IO pad利用逻辑仿真器对完成的新的TE系统进行编译，发现错误并改正,55,IP集成：RTL设计过程如何开始IP集成55

40、,RTL设计：第一步,我们已经对提供的pci bridge IP进行了独立验证，下面我们就要把这个IP集成到TE系统中来该IP是Verilog描述，Create a folder $TURBO/srcX2/vlog/pci然后Copy the PCI-Bridge code and the Amba-Wishbone wrapper there下面在该目录下进行IP集成,56,RTL设计：第一步我们已经对提供的pci bridge IP,RTL设计：第二步,需要实现的是黄色框内的内容，例化的过程可以参考其他IP的集成方法，如USB模块，也是通过ambaWbWrapper连接到amba总线的,P

41、CI Bridge,WishboneSlave,WishboneMaster,PCIInitiator,PCITarget,PCIArbiter,PCITarget,AmbaWishboneWrapper,Amba Bus,Amba_pci.v,Testbench,PCI_OUTPUT,PCI Bus,57,RTL设计：第二步需要实现的是黄色框内的内容，例化的过程可以,RTL设计：第二步,在pci目录中建立一个verilog文件：amba_pci.v，用来例化pci_bridge和ambaWbWrapper两个模块顶层模块为amba_pci，其端口需要连接到amba总线和pci总线,58,RT

42、L设计：第二步在pci目录中建立一个verilog文件：,RTL设计：第二步,顶层模块amba_pci：其中amba总线的端口为rsr_n和clk以及ahbSlaveIn和ahbSlaveOut两组slave接口信号这些信号同amba_usb.v中相同,59,RTL设计：第二步顶层模块amba_pci：PCI Brid,RTL设计：第二步,顶层模块为amba_pci：而pci总线接口的信号如图所示，只需要左半部分，即必须的信号即可具体的信号在pci_bridge32.v中其中双向IO口的信号需要使用双向IO单元，即TOP目录下的PCI66DGZ单元,60,RTL设计：第二步顶层模块为amba_

43、pci：PCI Bri,PCI IO signals and PCI Pads,Most PCI-Signals are bi-directionalCore has 3 wires for each signal: input, output and output_enableConnected to have a bi-directional IO Pad cellPCI Signal Integrity: Strict slew rate specificationsStrict input capacitance specificationsPCI-IO Pad requirement

44、sBidirectional, with slew limitationProvided by GSCLib_IO library: PCI66DGZ,pci_ad_oe_o,pci_ad_o,pci_ad_i,Core,IO PadcellPCI66DGZ,PC Board,Bonding Pad,61,PCI IO signals and PCI PadsMos,双向IO端口的连接,双向IO端口既可以作为输入又可以作为输出端口使用，因此节约了端口数目该IO单元在使能信号EN的控制下分别把来自电路core的信号由A输出到PAD上，或者把PAD上来的信号通过Y端输入到core中,62,双向IO

45、端口的连接双向IO端口既可以作为输入又可以作为输出端,双向IO端口的连接,例如amba_pci上的双向端口PAR，需要由3个信号连接到双向IO单元分别取名为PAR_2core,PAR_2pad,PAR_EN_n在后面的顶层设计中分别连接到双向IO单元的A，Y和EN端,63,双向IO端口的连接例如amba_pci上的双向端口PAR，需,RTL设计：第三步,在pci目录中建立一个verilog文件：amba_pci.v，用来例化pci_bridge和ambaWbWrapper两个模块PCI IP中包括构成FIFO的存储器模块，仿真过程中使用仿真模型，在pci_bridge/RAM目录下的RAM2P

46、_256x4_fun.vPut the RAM macro into $TURBO/srcX2/vlog/RAM,64,RTL设计：第三步在pci目录中建立一个verilog文件：,TE设计文件：硬件,srcX2目录TE的硬件代码Rtllib是仿真时用来存放库文件的，没有设计文件由于本设计中的IP来源不同，有的是VHDL描述，有的是Verilog描述，有的是二者都有Vhdl目录中是VHDL格式的IP，以及系统的顶层描述而verilog目录中是verilog格式的IP,65,TE设计文件：硬件srcX2目录TE的硬件代码65,第四步 RTL代码的编译,对集成后的pci模块进行编译发现错误并改正C

47、reate a “pci” folder in $TURBO/design/srcX2/rtllibThat is where the compiled database will be storedAdd the “pci” entry to $TURBO/design/srcX2/cds.libThat way the tools will know where to find the database,66,第四步 RTL代码的编译对集成后的pci模块进行编译66,第四步 RTL代码的编译,参照其他的shell脚本命令的形式Create a “compile_pci” in $TURBO

48、/exeAdd “compile_pci” to “compile_all_”Compile the Turbo Eagle to verifythat the PCI-Bridge compiles okaythat the overall code has not been broken,67,第四步 RTL代码的编译参照其他的shell脚本命令的形式6,第五步 修改TE顶层代码,完成对PCI IP的修改后，需要修改TE顶层代码，在系统中例化该IP，实现IP集成顶层为VHDL描述，在TOP目录，其中主要文件有：Trail_Asic.vhd:顶层文件，为整个设计的最顶层，其中例化了trial

49、_core.vhd和trail_padring.vhd两个文件中的模块Trail_core.vhd:包括KS_core.vhd和KS_iologic.vhd中的模块trail_padring.vhd:包含所有的IO单元KS_core.vhd:包含所有IP的结构Config:对系统中不同entity进行architecture配置PCI66DGZ.vhd,PDO08CDG.vhd,PDUDGZ.vhd分别为padring中的双向，输出和输入IO单元,68,第五步 修改TE顶层代码完成对PCI IP的修改后，需要修改,第五步 修改TE顶层代码,在KS_core.vhd中原来DES模块的位置例化新I

50、PCan use Amba-Bus channel #9 for the PCI-Bridge在KS_core.vhd中例化amba_pci结构在trail_core.vhd中更新KS_core结构在trail_padring.vhd中为amba_pci增加IO更新trail_asic.vhd中的端口和模块在config文件中，为amba_pci结构配置verilog并在vhdl/pci/amba_pci.vhd中定义entity amba_pci，可以参考usb结构,69,第五步 修改TE顶层代码在KS_core.vhd中原来DES,第六步 编译修改后的系统代码,利用compile_all命