EDA试验报告DES算法的verilog实现.docx

EDA试验报告一、实验工程名称DES算法二、实验目的与要求1.掌握DES的原理和设计方法。2,了解QUartUSII硬件电路设计流程，学会利用ModeIsim进展仿真。3.加深对自顶向下设计和分模块化的了解，学会模块化的设计方法。三、实验步骤（一）QES算法原理DES算法为密码体制中的对称密码体制，又被称为美国数据加密标准，是1972年美国IBM公司研制的对称密码体制加密算法。明文按64位进展分组，密钥长64位，密钥事实上是56位参与DES运算（第8、16、24、32、40、48、56、64位是校验位，使得每个密钥都有奇数个1）分组后的明文组和56位的密钥按位替代或交换的方法形成密文组的加密方法。其入口参数有三个:key、data、modeokey为加密解密使用的密钥，data为加密解密的数据，mode为其工作模式。当模式为加密模式时，明文按照64位进展分组，形成明文组，key用于对数据加密，当模式为解密模式时，key用于SiMSlI汰St”对数据解密。实际运用中，密钥只用到了64位中的56位，这样才具有高的安全性。DES算法把64位的明文输入块变为64位的密文输出块，它所使用的密钥也是64位，整个算法的主流程图如下：（二）、VeriIOgHDL实现原理拟采用模块化设计思想，根据DES算法的流程分模块设计实现各模块，自顶向下最终实现DES加密算法。各模块功能及实现如下所示:1.整体构造框架搭建，实现总体功能moduleDES(inputelk,inputdes_enable,inputreset,inputdes_modc,input1:64data_i,input1:64key_i,outputwire1:64data_o,outputready_o);wire3:0inter_num_curr;wire1:32R_i_var,L_i_var;wire1:56Key_i_var_out;wire1:64data_o_var_t;wire1:32R_i,LJ；wire1:32R_o,L._o；wire1:56Key_o;wire1:28CO,DO9TPIPl(.in(dataj),.L_i_var(L_i_var),.R_i_var(R_i_var);TP_niIP_ni(.in(data_o_var_t),.out(data_o);pc_lpc_l(.key_i(key_i),.C0(CO),.D0(DO);/F(R,K)des_fdes_f1(.elk(elk),.reset(reset),.des_mode(des_mode),.inter_num_i(inter_num_curr),.R_i(R_i),.L_i(L_i),.Key_i(Key_i_var_out),.R_o(R_o),.L_o(L_o),.Key_o(Key_o);/contral16F(R,K)contrlcontrl1(.data_o_var_t(data_o_var_t),.inter_num_curr(inter_num_curr),.Key_i_var_out(Key_i_var_out),.R_i(R_i),.L_i(L_i),.rcady_o(ready_o),.L_o(L_o),.R_o(R_o),.R_i_var(R_i_var),.L_i_var(L_i_var),.Key_o(Key_o),.CO(CO),.DO(DO),.clk(clk),.reset(reset),.des_enable(des_enable);endmodulemoduleIP(input1:64in,output1:32L_i_var,output1:32R_i_var);assignL_i_var,R_i_var)=in58,in50,in42,in34,in26,in18,in10,in2,in60,in52,in44,in36,in28,in20,in12,in4,in62,in54,in46,in38,in30,in22,in14,in6,in64,in56,in48,in40,in32,in24,in16,in8,in57,in49,in41,in33,in25,in17,in9,inl,in59,in51,in43,in35,in27,in19,inll,in3,in61,in53,in45,in37,in29,in21,in13,in5,in63,in55,in47,in39,in31,in23,in15,in7;endmodulemoduleIPni(input1:64in,output1:64out);assignout=(in40,in8,in48,in16,in56,in24,in64,in32,in39,in7,in47,in15,in55,in23,in63fin31,in38,in6,in46,in14,in54,in22,in62,in30,in37,in5,in45,in13,in53,in21,in61,in29,in36,in4,in44,in12,in52,in20,in60,in28,in35,in3,in43,inll,in51,in19,in59fin27,in34,in2,in42,in10,in50,in18,in58,in26,in33,inl,in41,in9,in49,in17,in57,in25;endmodule3 .圈子秘钥的生成modulekey_get(input1:56pre_key,inputdes_mode,input3:0inter_num,outputwire1:48new_key,outputreg1:56out_key);regpre_key_0,pre_key_1;reg1:56pre_key_var;always©(*)beginif(des_mode=1,b)begincase(inter_num)4 ,d,4,dl,4'd8,4,dl5:beginpre_key_var=pre_key;pre_key_0=pre_key_varl;pre_key_var1:28=pre_key_var1:28<<1;pre_key_var28=pre_key_0;pre_key_0=pre_key_var29;pre_key_var29:56=pre_key_var29:56<<1;pre_key_var56=pre_key_0;end4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd9,4,dl0,4,dll,4,dl2,4,dl3,4,dl4:beginpre_key_var=pre_key;(pre_key_l,pre_key_0=pre_key_varl:2;pre_key_var1:28=pre_key_var1:28<<2;pre_key_var27:28=pre_key_l,pre_key_0);pre_key_l,pre_key_0=pre_key_var29:30;pre_key_var29:56=pre_key_var29:56«2;pre_key_var55:56=pre_key_l,pre_key_0);endendcaseendelsebegincase(inter_num)4,d:pre_key_var=pre_key;4,dl,4'd8,4,dl5:beginpre_key_var=pre_key;pre_key_0=pre_key_var28;pre_key_var1:28=pre_key_var1:28»1;pre_key_varl=pre_key_0;pre_key_0=pre_key_var56;pre_key_var29:56=pre_key_var29:56»1;pre_key_var29=pre_key_O;enddefault:beginpre_key_var=pre_key;pre_key_l,pre_key_O=pre_key_var27:28;pre_key_var1:28=pre_key_var1:28>>2;pre_key_var1:2=pre_key_l,pre_key_O;pre_key_l,pre_key_O=pre_key_var55:56;prc_kcy_var29:56=pre_key_var29:56>>2;pre_key_var29:30=pre_key_l,pre_key_0);endendcaseendout_key=pre_key_var;endassignnew_key=pre_key_var14,pre_key_var17,pre_key_var11,pre_key_var24,pre_key_var1,pre_key_var5,pre_key_var3,pre_key_var28,pre_key_var15,pre_key_var6,pre_key_var21,pre_key_var10,pre_key_var23,pre_key_var19,pre_key_var12,pre_key_var4,pre_key_var26,pre_key_var8,pre_key_var16,pre_key_var7,pre_key_var27,pre_key_var20,pre_key_var13,pre_key_var2,pre_key_var41,pre_key_var52,pre_key_var31,pre_key_var37,pre_key_var47,pre_key_var55,pre_key_var30,pre_key_var40,pre_key_var51,pre_key_var45,pre_key_var33,pre_key_var48,pre_key_var44,pre_key_var49,pre_key_var39,pre_key_var56,pre_key_var34,pre_key_var53,pre_key_var46,pre_key_var42,pre_key_var50,pre_key_var36,pre_key_var29,pre_key_var32;endmodule3.f函数的实现moduledesf(inputelk,inputreset,inputdesmode,input3:0internumi,input1:32R_i,input1:32Li,input1:56Key_i,outputreg1:32R_o,outputreg1:32L_o,outputreg1:56Keyo);reg1:32nextR;/reg31:0Rivar;wire1:48expandcdR;reg1:56prekey;reg1:48new_key_tmp;reg3:0internum;wire1:32p;reg1:48address_s;reg1:32Soutput;wire1:32Soutputwire;wire1:48newkey;wire1:56OUt_key;key_getkey_get(.pre_key(pre_key),.desmode(desmode),.internum(internum),.newkey(newkey),.outkey(out_key);sisboxl(.StagCI_input(address_sl:6),.stagel_output(Soutputwirel:4);s2sbox2(.Stagelinput(address_s7:12),.Stageloutput(Soutputwire5:8);s3sbox3(.Stagelinput(address_s13:18),.Stageloutput(Soutputwire9:12);s4sbox4(.Stagelinput(address_s19:24),.Stageloutput(Soutputwire13:16);s5sbox5(.Stagelinput(address_s25:30),.Stageloutput(Soutputwire17:20);s6sbox6(.Stagelinput(address_s31:36),.Stageloutput(Soutputwire21:24);s7sbox7(.Stagelinput(address_s37:42),.Stageloutput(Soutputwire25:28);s8sbox8(.Stagelinput(address_s43:48),.stagel_output(Soutputwire29:32);always(POSeClgCelkornegedgereset)beginif(reset=b)beginR_o<=32,d;1._o<=32,d;Key_o<=56>d;endelsebeginKey_o<=out_key;if(inter_num=4,bllll)beginR_o<=R_i;1.o<=nextR;endelsebeginR_o<=nextR;1.o<=Ri;endendendassignexpandedR=RJ32,R-il,R_i，R_i3,R.i4,R_i5,R_i4,R_i5,R_i6,R_i7,R_i8,R_i9,R_i8,R_i9,R_i10,R_i11,R_i12,R_i13,R_i16,R_i17,R_i18,R_i19,R_i20,R_i21,R_i20,R_i21,RJ22,R_i23,R_i24,R_i25,R_i24,R_i25,R_i26,R_i27,R_i28,R_i29,R_i28,R_i29,R_i30,R_i31,R_i32,R_i;assignp=Soutput16,Soutput7,Soutput20,Soutput21,Soutput29,Soutput12,Soutput28,Soutput17,Soutput1,Soutput15,Soutput23,Soutput26,Soutput5,Soutput18,Soutput31,Soutput10,Soutput2,Soutput8,Soutput24,Soutput14,Soutput32,Soutput27,Soutput3,Soutput9,Soutput19,Soutput13,Soutput30,Soutput6,Soutput22,Soutputfll,Soutput4,Soutput25;always©(*)beginpre_key=Keyi;inter_num=internumi;new_key_tmp=newkey;address_s=new_key_tmpCexpandedR;Soutput=Soutputwire;/9999999999nextR=(L_ip);endendmodule5.迭代控制程序的设计与代码modulecontrl(output1:64data_o_var_t,outputreg3:0inter_num_curr,outputreg1:56Key_i_var_out,outputreg1:32Ri,L_i,input input input input inputoutputregreadyo,1:32L_o,1:32R_o,1:32Rivar,L_i_var,1:56Keyo,1:28CO,DO,inputelk,reset,des_enable);reg3:0internumnext;assigndata_o_var_t=(readyo=bl)?L_o,Ro)64,hzzzzzzzzzzzzzzzz;always(POSedgeelkornegedgereset)if(reset=1,b)begininternumnext<=4'd0;internumcurr<=4'd0;ready_o<=b;endelseif(des_enable)beginif(ready_o=1,b)inter_num_curr<=internumnext;endalways(POSedgeelkornegedgereset)beginif(reset=b)ready_o<=b;elseif(internumcurr=4,dl5)readyo<=bl;elsereadyo<=b;endalways0(*)begincase(internumcurr)4,dbegin/readyo=b;R_i=R_i_var;1._i=L_i_var;Keyivarout=CO,DO);internumnext=4'dl;end4,dl:begin/readyo=b;R_i=R_o;1._i=L_o;Key_i_var_out=Keyo;internumnext=4'd2;end4,d2:begin/ready_o=b;R_i=R_o;1._i=L_o;Key_i_var_out=Keyo;internumnext=4'd3;end4'd3:begin/readyo=b;R_i=R_o;1._i=Lo;Key_i_VarOUt=Keyo;internumnext=4'd4;end4'd4:begin/readyo=b;R_i=R_o;1._i=L_o;Key_i_VajoUt=Keyo;internumnext=4'd5;end4'd5:begin/readyo=b;R_i=R_o;1._i=L_o;Key_i_var_out=Keyo;internumnext=4'd6;end4,d6:begin/ready_o=b;R_i=R_o;1._i=L_o;Key_i_var_out=Keyo;internumnext=4'd7;end4'd7:begin/readyo=b;R_i=R_o;1._i=Lo;Key_i_VarOUt=Keyo;internumnext=4'd8;end4'd8:begin/readyo=b;R_i=R_o;1._i=L_o;Key_i_VajoUt=Keyo;internumnext=4'd9;end4,d9:begin/readyo=b;R_i=R_o;1._i=L_o;Key_i_var_out=Keyo;internumnext=4'dl0;end4,diO:begin/ready_o=b;R_i=R_o;1._i=L_o;Key_i_var_out=Keyo;internumnext=4'dll;end4,dll:begin/readyo=b;R_i=R_o;1._i=Lo;Key_i_VarOUt=Keyo;internumnext=4'dl2;end4,dl2:begin/readyo=b;R_i=R_o;1._i=L_o;Key_i_VajoUt=Keyo;internumnext=4'dl3;end4,dl3:begin/readyo=b;Ri=Ro:1._i=L_o;Key_i_var_out=Keyo;internumnext=4'dl4;end4,dl4:begin/ready_o=1,b;R_i=R_o;1._i=L_o;Key_i_var_out=Key_o;internumnext=4'dl5;end4, dl5:if(readyo=b)beginR_i=R_o;1._i=L_o;Keyivarout=Key_o;/readyo=1,bl;endendcaseendendmodule6.S盒的设计与实现SI)modulesi(stagel_input,stagel_output);input5:0Stagelinput;output3:0Stageloutput;reg3:0Stageloutput;/BIT5andBITOis?/BIT1is?always(stagel_input)begincase(stagelinput)/synopsysfullcaseparallel_case0:stagel_output=4*dl4;1: stagel_output=4'd0;2: stagel_output=4*d4;3: stagel_output=4,dl5;4: stagel_output=4*dl3;5: stagel_output=4'd7;6: stagel_output=4*dl;7: stagel_output=4'd4;8: stagel_output=4*d2;9: stagel_output=4,dl4;10: stagel_output=4,dl5;11: stage!output=4'd2;12:Stageloutput=4,dll;13:Stageloutput二41dl3;14:stagel_output二4,d8;15:Stageloutput=4'cll;16:Stageloutput=4,cl3;17:stageIoutput二41diO;18:stagel_output二4,diO;19:Stageloutput=4'd6;20:Stageloutput=4,d6;21:stageIoutput二41dl2;22:stagel_output二4,dl2;60:Stageloutput=4'd5;61:Stageloutput=4,d6;62:stageIoutput二41d;63:stagel_output二4,dl3;endcaseendendmodule(三)、modelsim仿真moduletestbenchl;regelk,reset,des_enable,des_mode;reg63:0datai,keyi;wire63:0datao;wireready_o;DESdl(elk,des_enable,reset,desmodefdatai,key_i,datao,ready_o);initialelk=b;initialbegindesmode=bl;#400reset=1,b;des_enable=1,b;#7reset=bl;des_enable=bl;desmode=bl;datai=64,h3b98d2eeaeb60035;key_i=64>h0123456789abcdef;endalways#10clk=clk;endmodule四、实验结果与分析利用MOdeSim软件，建设工程，做出仿真结果。五、实验体会通过本次试验，我更加深刻理解了DES算法的原理与构造，并对其良好的加密性有了更深一步的理解。通过编写VerilogHDL代码实现DES算法，让我对EDA设计中模块化的设计思想有了更进一步的了解。同时，由于该算法有一定的难度，我也参照了网上的一些内容。并学习Modelsim的仿真方法，完成了该实验。这对我解决问题的能力有所提高。