数字集成电路分析与设计-第五章答案.docx
P5.1.Foreachproblem,restateeachBooleanequationintoaformsuchthatitcanbetranslatedintothepandn-complexofaCMOSgate.a. OUf=ABC+BD=ABC+BD=(A+C)(+D)b. Owr=AB+AC+BC=AB+AC+BC=(A+B)(a+C)(B+C)c. Out=A+B+CD+A=AB(C+D)+A=A+B+CD+A=A+B+CD)AP5.2.P5.3.First,converttheequationintoitspandn-complex.Out=(AB)C+BC=(A耳+AB)C+BC=(A8+AB)C+BC=(AB+A)c)(c)=(AB+AB)+c)(bc)=(AB+A+C)(+C)P5.4.Thetruthtableisgivenbelowintermsofvoltages.ThefunctionisF=ABABF00Vdd0Vdd0VDD00VddVdd0TheworsecaseVohisVddandtheworsecaseVolis0V.a. The Vol for the pseudo-NMOS (in 0.18m) is:y _/>$17_ l'Sa TCQXWp (匕;5尸一I 匕7)d = kN (Vdd-Vtn) =Vgsp-tp + EcpLpVSATWPLN (VDD MPI)P5.5.ThefirstcircuitisaNORgatewhilethesecondisaNANDgate.TheVolandVoncalculatedarefortheworst-casescenario.Tofindthis,assumeonlyonetransistorturnson,thisjustreducestoapseudo-NMOS/PMOSinverter,sotheothertransistorsarenotimportant.NMN(%/)-MpI+ECPLP)(yl)DV77v)v%Ljv(VDO_l%l)0VMMN-MpI+%A)(%-L)=DDW=B0T/I)2VddAjv(VDo-MPl+ECPLP)(Vdd-Vtn)(8×IO6)(0.2×104)(0.2×104)(1.8-0.5)2_-0.1(1.8)(270)(1.8-0.5+24(0.2)(1.8-0.5)-014m-14Sincetheminimumwidthis2yWemakethatthewidth.TheVohforthepseudo-PMOS(in0.18m)is:In(sat)=Ip(Iin)VSArCOXWN(VGSN_VTNy_4pG)X%(匕GPT/)%)PL)VGSN-VTN+ECNLNLN(1+7)%rrC叱V(Vj)Q-V77v)2MP%CWP(匕)”一°一MJ)(%/)一/)一"叫"")Vdd-V+EcnLnlJ1+½)0.2(104)(8x106)(1.8-0,5)2(70)(1.8-0,5)(0.18)-j1.8- 0.5+1.27(l+)Wp4.2%Thepseudo-PMOScircuitwillhavebiggerdevicesthanthepseudo-NMOS.P5.6.Thestepstosolvingthisquestionarethesameasthepseudo-NMOSquestioninChapter4.a. ForVoH,recognizethatVgs>=VforoperationsotheoutputcanonlybeashighasVdd-V.SinceVs0,bodyeffectmustbetakenintoaccountandthefullequationis:oh=VDL(吟。+Y(yJVsB+2以一J2°j)=%-(%+y(府前-网耐)=1.2-(.4+0.2(jb+0.88-5网)IterationproducesVoh=0.73V.b. ForVol,wemustfirstrecognizethattheworst-caseVoloccurswhenonlyoneofthepull-downtransistorsison.Nextweidentifytheregionsofoperationofthetransistors.Inthiscase,thepull-uptransistorisalwaysinsaturationandthepull-downismostlikelyinthelinearregionsinceitwillhaveahighinput(highVgs)andalowoutput(lowVds).Then,weequatethetwocurrentstogetherandsolveforVol:I1(sat)=I2(Iiri)“NG(%)2WWZGX(%f警)入%51-½ri+ECNL&(1+r)(0.13)(104 )(8×106)(1.2-½7l- 0.42)2(1.2-0.42) + 0.6(1)(270)(1.2-0.4-)½.l(1+)Usingaprogrammablecalculatororaspreadsheetprogram,Vol=0.205V.Thedecurrentwiththeoutputlowis:_%MvCt9(%S2-n2-t22)%S2DL邙诲_(1)(270)(1.6×10-6)(1.2-0.4-空)(0.205)二=46.5AThepowerwiththeoutputlowis:P=IdsVdd=(46.5A)(1.2V)=55.8WP5.7.SeeExample5.2whichisbasedontheNANDgate.ThisquestionisthesameexceptthatitaddressestheNORgate.Withbothinputstiedtogether,Wn=SAWp=8d-N+_1.8-0.5+(2)(0.5)_U/Vl+z1+2IntheSPICEsolution,thereasonwhytheresultsvaryforinpulAandBisduetobody-effect.P5.8.Thesolutionisshownbelow.NoticethatthereisnorelevancewiththelengthsandwidthsofthetransistorswhenitcomestoVoh,althoughtheythedomatterwhencalculatingVol.1.=%F=1.8÷0.5+0.31.8+0.88-(88)=2.5IVP5.9.Forfpm,weneedtosizethepull-upPMOSappropriately.IPLH=07RC=°7R%pCLCADW%=0.7%今GaW=O.7(3Om)肃Ij(100xIOF)=842ForVol:=1.08mAG(Lf)2(4.2x10)(8x106)Mx1(T6)(l2-(U)?Vg5-½.+EcpL1.2-0.4+(24)(0.1).WNMVeo(%-粤)二(270)(1.6x10Y)(1.20.4-岑)0.1S"一L,(+r)l1÷WUZ/=38.5=11%=3x774=2324(3stack)%=1554(2stack)1.ZP5.10.Thecircuitisshownbelow:p-complex(dualofn)PLli07RC=REQPCLOADw,=0.7%P-LCLOAD=0.7(30×103)(50,7)(75×10-'5)=634tpHL=RC-07REQNT7CLOAD×10,5) = 26.6272W=07n*。皿=07(1Z5x103)(75Becausethenumberoftransistorsinseriesismorethanone,wemustmultiplythewidthsbytheappropriatenumber.Here,alltheNMOStransistorswillhaveawidthof54A.ThePMOStransistorswillhavewidthsof1262and190A,respectively.P5.11.Weestimatethedepoweranddynamicswitchingpowerforthisproblem.a. Thecircuit,sdepowercanbecomputedbycomputingthedecurrentwhentheoutputislow.ThisisgivenbyIds=550uAu11iX0.1um=55uA.ThenPdc=66uWwhentheoutputislow.b. ItsdynamicpowercanbecalculatedbysimplyusingtheequationPdxn=aCVDf.Therefore,Pdy11=(50fF)(Vdd-Vtn)(Vdd)(100MHz)=4.4uW.P5.12.Thepseudo-NMOSinverterhasstaticcurrentwhentheoutputislow.Wecanestimateitas:,.(Sm=3-J=(。“2(8Xw(I6*)(L2-04)2=25VGS-VT+EcpL1.2-0.4+(24)(0.1)ThentheaveragestaticpowerisPstat=(25.6uA)(1.2)/2=15.4uW.ThedynamicpowerisPi=CVDDVswingfavg=(50fF)(1.2)(1.1)favgassumingthatVolisO.IV.FortheCMOSinverter,thestaticpowerisalmostzero:PSIal=ISubVDD.Itisfarlessthanthepseudo-NMOScase.ThedynamicpowerPdyn=CVDiyswingfairg=(50fF)(1.2)2favgisslightlylargerthanthepseudo-NMOScase.Pseudo-NMOSP5.13.Modeldevelopmenttocomputesc.P5.14.Theenergydeliveredbythevoltagesourceis:0000JVDDEsource=igw=vddcl号dt=dvc=CMoOGo0000VDD/2纥即=Jia)y"=jG力=CJUH%=G-OOGOZAscanbeseen,onlyhalftheenergyisstoredinthecapacitor.Theotherhalfwasdissipatedasheatthroughtheresistor.P5.15.Theaveragedynamicpowerdoesnotdependontemperatureifthefrequencystaysthesame.However,theshort-circuitcurrentwillincreaseastemperatureincreases.Inaddition,thesubthresholdcurrentincreasesastemperatureincreases.Sotheoverallpowerdissipationwillbehigher.P5.16.Thecircuitisshownbelow.ThedelayshouldincorporatebothQandQbsettlingin400ps.AllNMOSandPMOSdevicesarethesamesizeinbothNANDgates.tp=fPHL+tPLH=°7RvpCload+DOWNLOD=LOADJ7Gq""+2R"）Wu/07ClMJR岬L+2%LW=IPlmRLPIR2Lneqpwpei,nv）0.7（100.10,5）（30.103）（0.1）+2（12.5.103）（0.1）400.1012P5.17.ThesmallglitchinJpropagatesthroughtheflopeventhoughitissmall.ThisisduetothefactthattheJK-flopofFigure5.20hasthe1'scatchingproblem.P5.18.ThesmallglitchinJdoesnotpropagatethroughtheflopsincetheedge-triggeredconfigurationdoesnothavea1,scatchingproblem.P5.19.Thepositive-edgetriggeredFFisasfollows:(a)WithCK=D=OandS=R=1,theoutputsare
