RF射频电路设计英文课件Lecture09-RFICandSOC.ppt

Lecture 9,Richard Li,2009,1,1.Interference and Isolation o Existence of Interference in Circuitry o Definition and Measurement of Isolation o Main Path of Interference in a RF Module o Main Path of Interference in a IC Die2.Shielding for a RF Module by a Metallic Shielding Box3.Strong Desirability to Develop RFIC4.Interference Going Along IC Substrate Path o Experimentation o Trench o Guard Ring5.Solution for Interference Coming from the Sky6.Common Grounding Rules for RF Module and RFIC Design o Grounding of Circuit-branches or Blocks in Parallel o DC Power Supply to Circuit-branches or Blocks in Parallel7.Bottlenecks in RFIC o Low Q Inductor and Possible Solution o“Zero”Capacitors o Bonding Wires8.Prospect of SOC9.What is Next?Appendixes o Notes about RFIC layout o Calculation of Quarter Wavelength o Progress of Electronic Industry,Lecture 9:RFIC&SOC Richard Chi-Hsi Li 李缉熙 Email:,Lecture 9,Richard Li,2009,2,o Existence of Interference in Circuitry,1.Interference and Isolation,o Definition and Measurement of Isolation,Isolation=-Attenuation of interference.,dB,dB,Lecture 9,Richard Li,2009,3,o Main Path of Interference in a RF Module,o Main Path of Interference in a IC Die,*From the sky!,*From the“ground”-the substrate!,Lecture 9,Richard Li,2009,4,o Definition and Measurement of Isolation o Main Path of Interference in a RF Moduleo Main Path of Interference in a IC Die,Lecture 9,Richard Li,2009,5,2.Schielding for a RF Module by a Metallic Shielding Box,Lecture 9,Richard Li,2009,6,3.Strong Desirability to Develop RFIC,The great advantages of the IC are:Greatly reduced cost,down by at least 10 times;Greatly reduced size,down more than 1000 times;Greatly enhanced reliability of product,by at least 100 times.,Lecture 9,Richard Li,2009,7,4.Interference Going Along IC Substrate Path,o Experimentation,Lecture 9,Richard Li,2009,8,Table 1 Interference attenuation or isolation when interference signal goes along IC substrate pathS21-40 dB,when f=10 MHz,S21-30 dB,when f=100 MHz,S21-20 dB,when f=1000 MHz,Lecture 9,Richard Li,2009,9,o Trench,Figure 5 Trenching of a RF block is to dig a deep ditch encompassing the RF block,Main PCB,One RF block,Externalinterferencesource,IC substrate,A deep ditch,Internalinterferencesource,Lecture 9,Richard Li,2009,10,o Guard Ring,Lecture 9,Richard Li,2009,11,Table 2 Comparison of interference attenuation or isolation between the cases with and without P+guard ring Without P+guard ringWith P+guard ring Frequency S21-40 dB,-80 to-70 dB,10 MHz,S21-30 dB,-60 to-55 dB,100 MHz,S21-20 dB,-40 dB,1000 MHz.,Lecture 9,Richard Li,2009,12,Table 1 Typical width of guard ring and spacing between guard rings in a RFIC layoutItem Value.Spacing between RF block and P+guard ring,S1=10 m,Spacing between P+guard ring and deep N-well,S2=1 m,Width of P+guard ring,WP=10 m,Width of deep N-well guard ring,WN=10 m.,Lecture 9,Richard Li,2009,13,5.Solution for Interference Coming from the Sky,Lecture 9,Richard Li,2009,14,Lecture 9,Richard Li,2009,15,6.Common Grounding Rules for RF Module and RFIC Design,o Grounding of Circuit-branches or Blocks in Parallel,Lecture 9,Richard Li,2009,16,Lecture 9,Richard Li,2009,17,o DC Power Supply to Circuit-branches or Blocks in Parallel,Lecture 9,Richard Li,2009,18,Lecture 9,Richard Li,2009,19,7.Bottlenecks in RFIC Design,o Low Q Inductor and Possible Solution,Spiral inductor,Lecture 9,Richard Li,2009,20,Skin effect,*Possible reasons of Low Q value,For copper,0.66 m,when frequency=10 GHz,6.6 m,when frequency=100 MHz.,T 0.1 m.(Thickness of the metal layer in IC),Unfortunately,the experiments indicate that the thin thickness of the metal layer is not the main reason that brings about the low Q value of the IC spiral inductor.,2)Attenuation due to the Existence of Substrate,Lecture 9,Richard Li,2009,21,3)Flux Leakage,Lecture 9,Richard Li,2009,22,4)Flux Cancellation,Lecture 9,Richard Li,2009,23,*Possible Solution of Low Q Value,-Compensation of negative resistance,However,it is not so simple in actual engineering design.The difficult points are:Generating a negative resistance;Ensuring that there is not negative resistance outside the expected bandwidth;The remained negative resistance inside the bandwidth must be kept below a small positive value;Reducing current consumption of generating negative resistance,which is usually done by an active device;Handling the noise generated due to the existence of the active device.,Lecture 9,Richard Li,2009,24,o“Zero”Capacitors,o Bonding Pad&Wires,Lecture 9,Richard Li,2009,25,8.Prospect of SOC,o Remove All the Bottlenecks in RFIC Design,The main bottlenecks in RFIC design are:Enhancing the low Q value of the spiral inductor;Developing a“zero”capacitor directly on the RFIC chip;Modeling the bonding wire with higher accuracy.,o Continue to Study Isolation,Studying isolation between RF blocks,Studying isolation between digital blocks.,Studying isolation between RF and digital blocks.,Lecture 9,Richard Li,2009,26,9.What is Next?,Lecture 9,Richard Li,2009,27,Appendixes,o Runner,*Length and width,A.1 Notes About RFIC Layout,*Multiple runners or curves in parallel,*Style of runner:As short as possible,*Smooth of the runner:As smooth as possible,*Placement of runners:Do perpendicular,not parallel as possible,*Corner of the runner:As smooth as possible,Lecture 9,Richard Li,2009,28,*Runners in parallel,*Runner in parallel with grounded edge,Lecture 9,Richard Li,2009,29,*Style of runner,“Nice looking”-NO!“E-W,S-N”-NO!,As short as possible-Yes!,A,B,A,B,Figure A.5 Two runner styles from A to B.,Lecture 9,Richard Li,2009,30,Lecture 9,Richard Li,2009,31,*Comparison of even and un-even runners,l,A,B,W0,ZO,ZL,(a)An even runner:W0=6 m,Z0=50.2 ohm,l=100 m,C,D,W1,W0,l/2,l/2,Z0,Z1,ZL,(b)An uneven runner:W0=30 m,Z0=21.2 ohm,l/2=50 m,W1=6 m,Z1=50.2 ohm,l/2=50 m,ZC=48.4 j7.9 ohm,ZL=50+j0 ohm,ZA=50+j0 ohm,ZL=50+j0 ohm,Additional Capacitor:In seriers:-j7.9 ohm=20.15 8.39 3.47 2.01 pF 1.0 2.4 5.8 10.0 GHzIn parallel:-j7.9 ohm=20.15 8.39 3.47 2.01 pF 1.0 2.4 5.8 10.0 GHz,Figure A.9 Comparison of impedance between even and uneven runner,Lecture 9,Richard Li,2009,32,*Summary about runners,Smoothly Perpendicular from each other as possible As short as possible,Lecture 9,Richard Li,2009,33,o Parts,*Device:Not“dragon”,but square!,But square!,Lecture 9,Richard Li,2009,34,*Inductor:Be care of the coupling!,D d1,d2 Add guard ring,Lecture 9,Richard Li,2009,35,*capacitor,(b)Study of capacitor with high capacitor/area is in progress.,Capacitor in RFIC is currently limited by its area,It is ruled less than about 20 pF,Figure A.14 Area of capacitor is one of important R&D projects at present,*Resistor,In order to enhance the tolerance,.10 identical resistors connected in parallel to form a resistor,Lecture 9,Richard Li,2009,36,o Parts must be located in a symmetrical way for differential circuit.o Via:The smaller the hole,The higher the inductance and resistance!o Free space is OK.Dont try to cover all the free space with grounding metal!,Lecture 9,Richard Li,2009,37,*Ideal number:1*Key issue:variable components by means of trimming or variable components by means of switching(Rather than switching,the trimming is to be preferred.),o How many times of tape-out?,Device,Lecture 9,Richard Li,2009,38,Capacitor,Resistor,Inductor,Lecture 9,Richard Li,2009,39,*Example:Layout for PA+LNA+Antenna SW.,Figure A.17 An example of RFIC layout with variable parts,Lecture 9,Richard Li,2009,40,o Pin distribution,o Via,*Insert“GND”pad in the middle of differential pair pads.,*Insert“GND”pads between two groups of pads,which correspond to two blocks respectively,Lecture 9,Richard Li,2009,41,A.2 Calculation of Quarter Wavelength,F/cm,nH/cm,F/cm,where Cmsl=Capacitance per unit length in respect to the substrate,W=Width if micro strip line Xint=Thickness of oxide layer,ox=Electric permittivity of the silicon-oxide layer,and Lmsl=Self-inductance per unit length along the runner,Xsi=Thickness of silicon substrate,Lecture 9,Richard Li,2009,42,Lecture 9,Richard Li,2009,43,W,m C,pF/cm L,nH/cm Freq,Hz QWL,mm l,5o,m Freq,Hz QWL,mm l,5o,m Freq,Hz QWL,mm l,5o,m Freq,Hz QWL,mm l,5o,m,Table A.1 Quarter wavelength(QWL)on RFIC die by CMOS,1 1.45 16.59 1.0E+09 16.09 894 2.4E+09 6.71 373 5.8E+09 2.77 154 10.0E+09 1.61 89,22.24 15.20 1.0E+09 13.55 753 2.4E+09 5.65 314 5.8E+09 2.34 130 10.0E+09 1.36 75,33.00 14.39 1.0E+09 12.04 669 2.4E+09 5.02 279 5.8E+09 2.08 115 10.0E+09 1.20 67,4 3.73 13.82 1.0E+09 11.01 612 2.4E+09 4.59 255 5.8E+09 1.90 105 10.0E+09 1.10 61,54.45 13.37 1.0E+09 10.25 569 2.4E+09 4.27 237 5.8E+09 1.77 98 10.0E+09 1.02 57,10 7.98 11.98 1.0E+09 8.08 449 2.4E+09 3.37 187 5.8E+09 1.39 77 10.0E+09 0.81 45,15 11.46 11.17 1.0E+09 6.99 388 2.4E+09 2.91 162 5.8E+09 1.20 67 10.0E+09 0.70 39,20 14.93 10.60 1.0E+09 6.29 349 2.4E+09 2.62 145 5.8E+09 1.08 60 10.0E+09 0.63 35,30 21.84 9.79 1.0E+09 5.41 300 2.4E+09 2.25 125 5.8E+09 0.93 52 10.0E+09 0.54 30,40 28.75 9.21 1.0E+09 4.86 270 2.4E+09 2.02 112 5.8E+09 0.84 47 10.0E+09 0.49 27,50 35.66 8.77 1.0E+09 4.47 248 2.4E+09 1.86 104 5.8E+09 0.77 43 10.0E+09 0.45 25,100 70.17 7.38 1.0E+09 3.47 193 2.4E+09 1.45 80 5.8E+09 0.60 33 10.0E+09 0.35 19,60 42.56 8.40 1.0E+09 4.18 232 2.4E+09 1.74 97 5.8E+09 0.72 40 10.0E+09 0.42 23,75 52.92 7.96 1.0E+09 3.85 214 2.4E+09 1.61 89 5.8E+09 0.66 37 10.0E+09 0.39 21,200 139.17 6.00 1.0E+09 2.74 152 2.4E+09 1.14 63 5.8E+09 0.47 26 10.0E+09 0.27 15,500 346.18 4.22 1.0E+09 2.07 115 2.4E+09 0.86 48 5.8E+09 0.36 20 10.0E+09 0.21 11,Assuming that Xint=0.5 m,Xsi=500 m,and ox=3.45x10-13 F/cm,Note:l,5o,m=Length of runner corresponding to phase shift 5o.,Lecture 9,Richard Li,2009,44,Lecture 9,Richard Li,2009,45,9A.3 Progress of Electronic Industry,o Evolution,o Why people are focusing on RFIC at present?,*Technology for logic or digital IC with low data rate is OK;,*Technology for RFIC is still in the development phase;,*Technology for logic or digital IC with high data rate must be based on RFIC Technology.,Lecture 9,Richard Li,2009,46,CompanyMotorolaPhilipsTek/MaximHarrisAD/IBMTechnologyMOSIC-5QB1C1QUICKCHIP-8UHF-1SiGeBiCmos85GST-2C-PIft(NPN)12/12 GHz13 GHz12/27/12 GHz8.6 GHz50 GHzft(PNP)700/50M200MHz8.5G/50M8.5GHz 4GHzStatusProProPro/DevProDevCycle time50 days90 days30-70 days90 days90 daysRiskM-H/M-HML/M-H/L-MM-HM-HM-H$/wafer$1.2k/2kTBD$10kTBD$2kDesign sys.Cadence-QUICKICFASTRACSPICERF ICMC13142SA601/6203600,o RFIC development,Table A.2 Early status of RF IC development(1995 1996),Table A.3 Performance of RF front end IC development(1996),Company(Motorola)(Philips)ChipMC13142*)SA601*)LNAMixerLNA MixerPower supply3 v3 v3 v3 vCurrent drain3.5 mA4.0 mA3.0 mA4.4 mAGain12 dB6 dB11.5 dB6 dBNoise Figure2.0 dB10 dB1.6 dB9.5 dBIIP3-4 dBm4 dBm-2 dBm-2dBmIsolation*)45 dB40 dB*)1 GHz;*)881 Mhz;*)From LNA output to Mixer RF input.,Lecture 9,Richard Li,2009,47,Table A.4 Status of RFIC development(1998 2000),IBM(1998)SiGe BiCMOSSGRF0100(LNA)SGRF4111(VCO)SGRF2113(LNA+IR Mixer*)Vcc=3vVcc=3vVcc=3vIcc=5.5 mAIcc=10.0 mAIcc=15.0 mAf=1.9 GHzf=880/1850 MHzf=900/1900 MHzG=12.5 dBk=120 MHz/vG=22 dBNF=1.2 dB SBN=-92 dBc/HzNF=3 dBIIP3=13 dBm 20 kHz offsetIIP3=-12 dBmPLO=-10 dBmIso=20 dB*)PLO=-10 dBm,IF=400 MHz,Load_IF=600 ohm.,Infineon(2000)LNAPAPrescalar*)Vcc=3vVcc=2.8vVcc=2.3v-Icc=11.7 mAf=1.9 GHzf=900 MHzf=20 GHzG=28 dBEff=54%Wic=0.5u NF=1.1 dB Pout=3.2 watts*)Digital,Processing fT ReliabilityCostSiGe BiCMOS50-75 GHz OKL+Si CMOS15-25 GHz GoodLSi BiCMOS15-35 GHz GoodMGaAs MOS50-90 GHz OK-H,RF Micro Devices(March 2001)Sony(January 2001)2 LNAs/3 MixersSoftware Radio 500 MHz to 9 GHzRF2489 Mainly for WCDMA,also for GPSG:15 to 18 dBQualcom(February 2001)NF-1.1 to 1.3 dB RF T5200,RFR52000 Mainly for WCDMA IIP3=-4 to+12 dBmCost=$2.31 for 100k pieces Silicon Labs.In Austin(March 2001)RF IC chip,CMOS Mainly for GSM/GPRS,Table A.5 RFIC covers all of RF/MW blocks except filter,such as,Synthesizer,VCO,RF PA,Lecture 9,Richard Li,2009,48,Table A.6 WLAN IEEE 802.11a system,RFIC(2000 2003),CompanyIntersilResonextBermaiAtherosFrequency band5.15-5.25 5.15-5.25 5.15-5.25 5.15-5.25 5.25-5.35 5.25-5.35 5.25-5.35 5.25-5.35 5.725 5.825RxDual-Conv.Zero IF Dual-Conv.TxPA for indoor18 dBm PA22 dBm PAExt.PAExt.PAW/O Ext.PAW/O Ext.PAPackageMLFMLFLLPCProcessingCMOSo.18uCMOS0.18uCMOS0.25uCMOSSiGeBiCMOSNumber of chips 3+PA+SAW212,