嵌入式系统接口设计与应.ppt

嵌入式系统设计与应用,STM32F103MCU本课程的主要内容,主要内容,Cortex-M3的总结STM32F系列的特点STM32F103系列的特点STM32F103的概述STM32F103的外特性STM32F103的内特性STM32F103的SFRSTM32F103的应用,主要参考资料,STM32F103xxx_Datasheet.pdfSTM32F103xxx_Reference_Manual.pdfSTM32F103xxx_Library_Manual.pdfRVMDK 3.2,Cortex-M3的总结,Cortex-M3的总结CM3NVIC,Cortex-M3的总结,Cortex-M3的特性Cortex-M3 block diagram,Cortex-M3的总结,Cortex-M3的特性Processor coreARMv7-M architecture.The main features:Thumb-2 instruction set subset.Harvard Architecture with data load/store.Three-stage pipeline.Single cycle 32-bit multiply.Hardware divide.Thumb and Debug states.Handler modes and Thread modes.without the overhead of state saving and restoration between interrupts.Interruptible-continued LDM/STM,PUSH/POP.ARMv6 compatible BE8 and LE access support.ARMv6 compatible unaligned access support.,Cortex-M3的总结,Cortex-M3的特性Processor coreARMv7-M architecture.The main features:Low latency ISR entry and exit.Processor state saving and restoration,with no instruction fetch overhead.Exception vector is fetched from memory in parallel with the state saving,enabling faster ISR entry.Support for late arriving(迟来)interrupts.Tightly coupled interface to interrupt controller enabling efficient processing of late-arriving(迟来)interrupts.Tail-chaining(尾连)of interrupts,enabling back-to-back(背靠背)interrupt processing,Cortex-M3的总结,Cortex-M3的特性Processor coreRegisters The processor contains:13 general purpose 32-bit registers,R0 to R12Link Register(LR)-R14Program Counter(PC)-R15Program Status Register,xPSRtwo banked SP registers.-R13,Cortex-M3的总结,Cortex-M3的特性Processor coreMemory interfaceThe processor has a Harvard interface to enable simultaneous instruction fetches with data load/stores.Memory accesses are controlled by:A separate Load Store Unit(LSU)that decouples load and store operations from the Arithmetic and Logic Unit(ALU).A 3-word entry Prefetch Unit(PFU).One word is fetched at a time.This can be two Thumb instructions:one word-aligned Thumb 32-bit instruction;the upper/lower halfword of a halfword-aligned Thumb 32-bit instruction with one Thumb instruction,or the lower/upper halfword of another halfword-aligned Thumb 32-bit instruction.,Cortex-M3的总结,Cortex-M3的特性Processor coreNVICThe NVIC is tightly coupled to the processor core.This facilitates low latency exception processing.The main features include:a configurable number of external interrupts,from 1 to 240a configurable number of bits of priority,from three to eight bitslevel and pulse interrupt supportdynamic reprioritization of interruptspriority groupingsupport for tail-chaining of interruptsprocessor state automatically saved on interrupt entry,and restored on interrupt exit,with no instruction overhead.,Cortex-M3的总结,Cortex-M3的特性Processor coreBus matrixThe bus matrix connects the processor and debug interface to the external buses.The bus matrix interfaces to the following external buses:ICode bus.This is for instruction and vector fetches from code space,it is a 32-bit AHB-Lite bus.DCode bus.This is for data load/stores and debug accesses to code space.it is a 32-bit AHB-Lite bus.System bus.This is for instruction and vector fetches,data LD/ST and debug accesses to system space.This is a 32-bit AHB-Lite bus.PPB.This is for data LD/ST and debug accesses to PPB space.This is a 32-bit APB(v3.0)bus.,Cortex-M3的总结,Cortex-M3的特性Processor coreBus matrixThe bus matrix also controls the following:Unaligned accesses.The bus matrix converts unaligned processor accesses into aligned accesses.Bit-banding.The bus matrix converts bit-band alias accesses into bit-band region accesses.It performs:bit field extract for bit-band loads;atomic read-modify-write for bit-band stores.Write buffering.The bus matrix contains a one-entry write buffer to decouple bus stalls from the processor core.,Cortex-M3的总结,Cortex-M3的特性Processor coreDWTYou can configure the implementation to include a DWT.If present,you can configure the DWT to incorporate the following debug functionality:four comparators that you can configure either as a hardware watchpoint,an ETM trigger,a PC sampler event trigger,or a data address sampler event triggerseveral counters or a data match event trigger for performance profiling(性能分析)configurable to emit PC samples at defined intervals,and to emit interrupt event information.,Cortex-M3的总结,Cortex-M3的特性Processor coreETMYou can configure the system at implementation to include an ETM.This is a low-cost trace macrocell that supports instruction trace only.WICYou can configure the implementation to include a Wake-up Interrupt Controller(WIC).,Cortex-M3的总结,Cortex-M3的编程模式About the programmers modelThe processor architecture is the ARMv7-M.Instructions architecture is the Thumb-2.Operating modes：The processor supports two modes of operation,Thread mode and Handler mode:Thread mode is entered on Reset,and can be entered as a result of an exception return.Privileged and User(Unprivileged)code can run in Thread mode.Handler mode is entered as a result of an exception.All code is privileged in Handler mode.,Cortex-M3的总结,Cortex-M3的编程模式About the programmers modelOperating statesThe processor can operate in one of two operating states:Thumb-2 state.This is normal execution running 16-bit and 32-bit halfword aligned Thumb instructions.Debug State.This is the state when in halting debug.,Cortex-M3的总结,Cortex-M3的编程模式Privileged access and user accessCode can execute as privileged or user:User(Unprivileged)execution limits or excludes access to some resources.Privileged execution has access to all resources.Handler mode is always privileged.Thread mode can be privileged or unprivileged.When Thread mode has been changed from privileged to user,it cannot change itself back to privileged.Only a Handler can change the privilege of Thread mode.Handler mode is always privileged.,Cortex-M3的总结,Cortex-M3的编程模式Privileged access and user accessMain stack and process stackOut of reset,all code uses the main stack.An exception handler such as SVC can change the stack used by Thread mode from main stack to process stack by changing the EXC_RETURN value it uses on exit.All exceptions continue to use the main stack.The stack pointer,r13,is a banked register that switches between SP_main and SP_process.Only one stack,the process stack or the main stack,is visible,using r13,at any time.It is also possible to switch from main stack to process stack while in Thread mode by writing to CONTROL1 using the MSR instruction,in addition to being selectable using the EXC_RETURN value from an exit from Handler mode.,Cortex-M3的总结,Cortex-M3的编程模式RegistersThe processor has the following 32-bit registers:13 general-purpose registers,r0-r12Stack point alias of banked registers,SP_process and SP_mainLink register,r14Program counter,r15One program status register,xPSR.Figure shows the processor register set.,Cortex-M3的总结,Cortex-M3的编程模式RegistersThe processor has the following 32-bit registers:13 general-purpose registers,r0-r12Stack point alias of banked registers,SP_process and SP_mainLink register,r14Program counter,r15One program status register,xPSR.Figure shows the processor register set.,Cortex-M3的总结,Cortex-M3的编程模式RegistersGeneral-purpose registersThe general-purpose registers r0-r12 have no special architecturally-defined uses.Most instructions that can specify a general-purpose register can specify r0-r12.Low registers Registers r0-r7 are accessible by all instructions that specify a general-purpose register.High registers Registers r8-r12 are accessible by all 32-bit instructions that specify a general-purpose register.Registers r8-r12 are not accessible by all 16-bit instructions.,Cortex-M3的总结,Cortex-M3的编程模式RegistersThe r13 have following special functions:Stack pointer Register r13 is used as the Stack Pointer(SP).Because the SP ignores writes to bits 1:0,it is autoaligned to a word,four-byte boundary.Handler mode always uses SP_main,but you can configure Thread mode to use either SP_main or SP_process.The r14 have following special functions:Link register Register r14 is the subroutine Link Register(LR).The LR receives the return address from PC when a Branch and Link(BL)or Branch and Link with Exchange(BLX)instruction is executed.,Cortex-M3的总结,Cortex-M3的编程模式RegistersThe r14 have following special functions:The LR is also used for exception return.At all other times,you can treat r14 as a general-purpose register.The r15 have following special functions:Program counter Register r15 is the Program Counter(PC).Bit 0 is always 0,so instructions are always aligned to word or halfword boundaries.,Cortex-M3的总结,Cortex-M3的编程模式RegistersSpecial-purpose Program Status Registers(xPSR)Processor status at the system level breaks down into three categories:Application PSRInterrupt PSRExecution PSRThey can be accessed as individual registers,a combination of any two from three,or a combination of all three using the Move to Register from Status(MRS)and MSR instructions.,Cortex-M3的总结,Cortex-M3的编程模式RegistersSpecial-purpose Program Status Registers(xPSR)Application PSRThe Application PSR(APSR)contains the condition code flags.Before entering an exception,the processor saves the condition code flags on the stack.You can access the APSR with the MSR(2)and MRS(2)instructions.Figure shows the bit assignments of the APSR.,Cortex-M3的总结,Cortex-M3的编程模式RegistersxPSR APSR,Cortex-M3的总结,Cortex-M3的编程模式RegistersxPSRInterrupt PSRThe Interrupt PSR(IPSR)contains the Interrupt Service Routine(ISR)number of the current exception activation.,Cortex-M3的总结,Cortex-M3的编程模式RegistersxPSR IPSR,Cortex-M3的总结,Cortex-M3的编程模式RegistersxPSR Execution PSRThe Execution PSR(EPSR)contains two overlapping fields:the Interruptible-Continuable Instruction(ICI)field for interrupted load multiple and store multiple instructions;the execution state field for the If-Then(IT)instruction,and the Thumb state bit(T-bit).Interruptible-continuable instruction field.Load Multiple(LDM)operations and Store Multiple(STM)operations are interruptible.The ICI field of the EPSR holds the information required to continue the load or store multiple from the point that the interrupt occurred.,Cortex-M3的总结,Cortex-M3的编程模式RegistersxPSR Execution PSRIf-then state field:The IT field of the EPSR contain the execution state bits for the If-Then instruction.Because the ICI field and the IT field overlap,load or store multiples within an If-Then block cannot be interrupt-continued.,Cortex-M3的总结,Cortex-M3的编程模式RegistersxPSR EPSR,Cortex-M3的总结,Cortex-M3的编程模式RegistersSaved xPSR bitsOn entering an exception,the processor saves the combined information from the three status registers on the stack.The stacked xPSR also contains information about whether the stack was 8-byte aligned or not depending on the value of STKALIGN in the Configuration Control Register.This information is stored in bit 9 of the xPSR on the stack,and it is a 1 if the stack was forced to be 8-byte aligned.,Cortex-M3的总结,Cortex-M3的编程模式Memory formatsThe processor views memory as a linear collection of bytes numbered in ascending order from 0.For example:bytes 0-3 hold the first stored wordbytes 4-7 hold the second stored word.The processor can access data words in memory in little-endian format or big-endian format.It always accesses code in little-endian format.,Cortex-M3的总结,Cortex-M3的编程模式Memory formatslittle-endian format,Cortex-M3的总结,Cortex-M3的编程模式Instruction set summaryThis section provides:a summary of the processor 16-bit instructionsa summary of the processor 32-bit instructions.略,Cortex-M3的总结,System ControlSummary of processor registersDescribes the registers that control functionality.It contains the following:Nested Vectored Interrupt Controller registersCore debug registers;System debug registers;Debug interface port registers;Memory Protection Unit registers;Trace Port Interface Unit registers;Embedded Trace Macrocell registers.,Cortex-M3的总结,System ControlSummary of processor registersDescribes the registers that control functionality.It contains the following:Nested Vectored Interrupt Controller registersCore debug registers;System debug registers;Debug interface port registers;Memory Protection Unit registers;Trace Port Interface Unit registers;Embedded Trace Macrocell registers.主要介绍NVIC,Cortex-M3的总结,NVICNVIC register mapThe NVIC space is split as follows:0 xE000E000-0 xE000E00F:Interrupt Type Register0 xE000E010-0 xE000E0FF:System Timer0 xE000E100-0 xE000ECFF:NVIC0 xE000ED00-0 xE000ED8F:System Control Block:CPUID System control,configuration,and status Fault reporting0 xE000EF00-0 xE000EF0F:Software Trigger Exception Register0 xE000EFD0-0 xE000EFFF:ID space.,Cortex-M3的总结,NVIC,Cortex-M3的总结,NVIC,Cortex-M3的总结,NVIC,Cortex-M3的总结,NVIC,Cortex-M3的总结,Memory MapDescribes the processor fixed memory map and its bit-banding feature.It contains the following sections:About the memory mapBit-bandingROM memory table,Cortex-M3的总结,Memory Map,Cortex-M3的总结,Memory Map,Cortex-M3的总结,Memory MapMemory region permissionsWBWA:Write back write allocate,Notes:Private Peripheral Bus and System space at 0 xE0000000-0 xFFFFFFFF are permanentlyXN.The MPU cannot change this.,Cortex-M3的总结,Memory MapBit-bandingThe processor memory map includes two bit-band regions.These occupy the lowest 1MB of the SRAM and Peripheral memory regions respectively.These bit-band regions map each word in an alias region of memory to a bit in a bit-band region of memory.The memory map has two 32-MB alias regions that map to two 1-MB bit-band regions:Accesses to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region.Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band region.,Cortex-M3的总结,Bit-bandingPrincipleThe mapping formula is:One-bit Mapping to One-Word!bit_word_offset=(byte_offset32)+(bit_number4)bit_word_addr=bit_band_base+bit_word_offsetwhere:Bit_word_offset is the position of the target bit in the bit-band memory region.Byte_offset is the number of the byte in the bit-band region that contains the targeted bit.Bit_number is the bit position(0-7)of the targeted bit.Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.Bit_band_base is the starting address of the alias region.,Cortex-M3的总结,Bit-bandingPrincipleFigure shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region:The alias word at 0 x23FFFFE0 maps to bit 0 of the bit-band byte at 0 x200FFFFF:0 x23FFFFE0=0 x22000000+(0 xFFFFF*32)+0*4.The alias word at 0 x23FFFFFC maps to bit 7 of the bit-band byte at 0 x200FFFFF:0 x23FFFFFC=0 x22000000+(0 xFFFFF*32)+7*4.The alias word at 0 x22000000 maps to bit 0 of the bit-band byte at 0 x20000000:0 x22000000=0 x22000000+(0*32)+0*4.The alias word at 0 x2200001C maps to bit 7 of the bit-band byte at 0 x20000000:0 x2200001C=0 x22000000+(0*32)+7*4.,Cortex-M3的总结,Bit-bandingFigure,Cortex-M3的总结,Bit-bandingDirectly accessing an alias regionWriting to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.Bit 0 of