基于VHDL的电子表设计.ppt

基于VHDL的电子表设计,邢安安,目录,电子表的系统分析和设计,计时器,状态机,闹钟寄存器,4,1,2,3,电子表顶层电路的实现,6,铃声管理模块,5,电子表的系统分析和设计,设计要求：设计一个电子表，可以用于显示时间丶设定闹钟和整点报时。电子表的输入设备是一个44的编码键盘，输出设备是用于显示的6位LED数码管丶若干LED指示灯以及蜂鸣器。,电子表的系统分析和设计,.开启或关闭整点报时和闹钟,.设置闹铃时间,在电子表计时状态下按下设置闹钟键（键），进入设定闹钟时间状态。其他操作与校时操作流程一样。,每按一下整点报时开关键（键），整点报时状态改变,每按一下闹钟开关键（键）闹钟状态改变,LED指示灯：计时状态，显示当前时间；校时和设闹状态，显示输入时间,用于界面设计,.校时操作,在电子表计时状态下按校时键（键）进入校时状态,使用数字键输入新的时间并按下确认键（键）,在校时状态下任何时刻按下取消键（键）可退出校时状态,电子表的系统分析和设计,闹钟时间寄存器,计时器,铃声管理,系统结构和模块划分,状态机,计时器,分频器,时间计数的频率为1Hz，而外部晶振频率为1MHz,所以需要1M分频计数器,计数器,时间计数器的目的是为了得到时间输出，因此需要每秒技术一次。,状态机,状态机模块是电子表的控制器，它给出其他模块的时序。状态机的输入信号是键盘模块的输出信号keyvalue,keypressed和functionkey。状态机的输出信号是缓存时间信号buffertime,闹钟时间加载信号alarmload，计时器时间加载信号timeload，闹钟开关状态alarmom和整点报时开关状态houralarmon。Time是由用户通过键盘输入的时间信号，可以送给闹钟寄存器和计时器。,状态机包括两部分：1.用于产生缓存时间信号buffertime，闹钟时间加载信号alarmload和计时器时间加载信号timeload，称这部分状态机为校时和设闹状态机。2.用于产生闹钟开关状态信号alarmon和整点报时开关状态信号houralarmom，称为闹钟和整点报时开关状态机。,闹钟和整点报时状态机,Text in here,Text in here,Text in here,闹钟寄存器,闹钟寄存器是一个带有并行加载功能的寄存器。其中clk是全局时钟，buffertime是并行加载的数据输入，alarmload为并行加载的控制输入，alarmtime为寄存器的输出。,Title in here,Title in here,Title in here,Title in here,A,B,C,D,铃声管理模块,闹钟铃声状态机,Alarm time=time,S0/0,S4/1,S2/0,S1/0,S3/1,Time(6)=1,Time(6)=0,Time(6)=1,Time(6)=0,alarmon=0,电子表顶层电路的实现,闹钟和整点报时状态机,校时和设闹状态机,闹钟寄存器,计时器,校时和设闹输出,闹铃管理模块,Contents,Contents,Contents,Contents,顶层文件,采用元件例化的方法将各个模块连接起来，组成电子表系统,顶层程序,library ieee;use ieee.std_logic_1164.all;use;entity clock_top isport(clk,keypressed,functionkey:in std_logic;keyvalue:in std_logic_vector(3 downto 0);displaytime:out std_logic_vector(23 downto 0);alarm_signal:out std_logic;alarmon,houralarmon:buffer std_logic);end clock_top;architecture rt of clock_top iscomponent statemachineport(clk,keypressed,functionkey:in std_logic;keyvalue:in std_logic_vector(3 downto 0);iscount,alarmload,timeload:out std_logic;buffertime:buffer std_logic_vector(23 downto 0);end component;component statemachine2port(clk,keypressed:in std_logic;keyvalue:in std_logic_vector(3 downto 0);alarmon,houralarmon:out std_logic);end component;,component counter port(clk,load:in std_logic;buffertime:in std_logic_vector(23 downto 0);time:out std_logic_vector(23 downto 0);end component;component alarmregport(clk,alarmload:in std_logic;buffertime:in std_logic_vector(23 downto 0);alarmtime:out std_logic_vector(23 downto 0);end component;component bellport(clk,houralarmon,alarmon:in std_logic;alarmtime,time:in std_logic_vector(23 downto 0);alarm_signal:out std_logic);end component;signal buffertime,time,alarmtime:std_logic_vector(23 downto 0);signal iscount,alarmload,timeload:std_logic;,beginsm1:statemachineport map(clk,keypressed,functionkey,keyvalue,iscount,alarmload,timeload,buffertime);sm2:statemachine2port map(clk,keypressed,keyvalue,alarmon,houralarmon);cnt:counterport map(clk,timeload,buffertime,time);reg:alarmregport map(clk,alarmload,buffertime,alarmtime);bl:bellport map(clk,houralarmon,alarmon,alarmtime,time,alarm_signal);process(iscount,time,buffertime)beginif(iscount=1)thendisplaytime=time;elsedisplaytime=buffertime;end if;end process;end rt;,计数器程序（1）,library ieee;use ieee.std_logic_1164.all;use;use;entity counter isport(clk,load:in std_logic;buffertime:in std_logic_vector(23 downto 0);time:out std_logic_vector(23 downto 0);end counter;architecture rt of counter iscomponent divider_1mport(clk:in std_logic;clk1s:out std_logic);end component;signal clk1s:std_logic;signal time_sig:std_logic_vector(23 downto 0);begin,u1:divider_1m port map(clk,clk1s);process(clk1s,clk)beginif(clkevent and clk=1)thenif(load=1)thentime_sig=buffertime;elseif(clk1s=1)thenif(time_sig(3 downto 0)=1001)thentime_sig(3 downto 0)=0000;if(time_sig(7 downto 4)=0101)thentime_sig(7 downto 4)=0000;if(time_sig(11 downto 8)=1001)thentime_sig(11 downto 8)=0000;if(time_sig(15 downto 12)=0101)thentime_sig(15 downto 12)=0000;if(time_sig(23 downto 16)=00001001)thentime_sig(23 downto 16)=00010000;elsif(time_sig(23 downto 16)=00011001)thentime_sig(23 downto 16)=00100000;elsetime_sig(23 downto 16)=time_sig(23 downto 16)+1;end if;,elsetime_sig(15 downto 12)=time_sig(15 downto 12)+1;end if;elsetime_sig(11 downto 8)=time_sig(11 downto 8)+1;end if;elsetime_sig(7 downto 4)=time_sig(7 downto 4)+1;end if;elsetime_sig(3 downto 0)=time_sig(3 downto 0)+1;end if;end if;end if;end if;end process;time=time_sig;end rt;,library ieee;use ieee.std_logic_1164.all;use;entity divider_1m isport(clk:in std_logic;clk1s:out std_logic);end divider_1m;architecture rt1 of divider_1m issignal cnt:integer range 0 to 999999;beginprocess(clk)beginif(clkevent and clk=1)thenif(cnt=cnthigh)thencnt=0;clk1s=1;elsecnt=cnt+1;clk1s=0;end if;end if;end process;end rt1;,计数器程序（2）,闹钟和整点报时,library ieee;use ieee.std_logic_1164.all;use;use;entity statemachine2 isport(clk,keypressed:in std_logic;keyvalue:in std_logic_vector(3 downto 0);alarmon,houralarmon:out std_logic);end statemachine2;architecture rt of statemachine2 istype state is(s_off,s_on);signal ps_alarmon,ns_alarmon,ps_houralarmon,ns_houralarmon:state:=s_off;beginprocess(clk)beginif(clkevent and clk=1)thenps_alarmon=ns_alarmon;ps_houralarmon=ns_houralarmon;end if;end process;process(ps_alarmon,keypressed,keyvalue),begin if(ps_alarmon=s_on)thenif(keypressed=1and keyvalue=1101)then ns_alarmon=s_off;else ns_alarmon=ps_alarmon;end if;alarmon=1;elseif(keypressed=1and keyvalue=1101)thenns_alarmon=s_on;elsens_alarmon=ps_alarmon;end if;alarmon=0;end if;end process;,process(ps_houralarmon,keypressed,keyvalue)beginif(ps_houralarmon=s_on)thenif(keypressed=1and keyvalue=1100)thenns_houralarmon=s_off;elsens_houralarmon=ps_houralarmon;end if;houralarmon=1;elseif(keypressed=1and keyvalue=1100)thenns_houralarmon=s_on;elsens_houralarmon=ps_houralarmon;end if;houralarmon=0;end if;end process;end rt;,闹钟寄存器,library ieee;use ieee.std_logic_1164.all;entity alarmreg isport(clk,alarmload:in std_logic;buffertime:in std_logic_vector(23 downto 0);alarmtime:out std_logic_vector(23 downto 0);end alarmreg;architecture rt of alarmreg isbeginprocess(clk)beginif(clkevent and clk=1)thenif(alarmload=1)thenalarmtime=buffertime;end if;end if;end process;end rt;,铃声管理,library ieee;use ieee.std_logic_1164.all;entity bell isport(alarmtime,time:in std_logic_vector(23 downto 0);alarmon,houralarmon,clk:in std_logic;alarm_signal:out std_logic);end bell;architecture rt of bell issignal alarm,houralarm:std_logic;type state is(s0,s1,s2,s3,s4);signal present_state,next_state:state:=s0;beginprocess(clk,alarmon)beginif(alarmon=0)thenpresent_state=s0;elsif(clkevent and clk=1)thenpresent_state=next_state;end if;end process;,process(present_state,time,alarmtime)begincase present_state iswhen s0=if(alarmtime=time)thennext_stateif(time(6)=1)thennext_state if(time(6)=0)then next_state if(time(6)=1)then next_state=s4;else next_state=present_state;end if;,when s4=If(time(6)=0)then next_state next_state=s0;end case;end process;process(present_state)begin if(present_state=s3 or present_state=s4)then alarm=1;else alarm=0;end if;end process;process(houralarmon,time)begin if(houralarmon=1and time(15 downto 0)=0000000000000000)then houralarm=1;else houralarm=0;end if;end process;alarm_signal=alarm or houralarm;end rt;,状态机,library ieee;use ieee.std_logic_1164.all;use;entity statemachine isport(clk,keypressed,functionkey:in std_logic;keyvalue:in std_logic_vector(3 downto 0);buffertime:buffer std_logic_vector(23 downto 0);iscount,alarmload,timeload:out std_logic);end statemachine;,architecture rt of statemachine istype state is(count,modifytime1,modifytime2,modifytime3,modifytime4,modifytime5,modifytime6,modifytime7,loadtime,setalarm1,setalarm2,setalarm3,setalarm4,setalarm5,setalarm6,setalarm7,loadalarm);signal present_state,next_state:state:=count;signal time_temp:std_logic_vector(23 downto 0);beginprocess(clk)beginif(clkevent and clk=1)thenpresent_state=next_state;end if;end process;process(keyvalue,keypressed,functionkey,present_state,clk)beginif(clkevent and clk=1)then,case present_state iswhen count=if(keypressed=1and keyvalue=1110)thennext_stateif(keypressed=1and keyvalue=1011)thennext_state=count;elsif(keypressed=1and keyvalue=0010)thennext_state=modifytime2;time_temp(23 downto 20)=keyvalue;elsenext_state=present_state;time_temp=time_temp;end if;,when modifytime2=if(keypressed=1and keyvalue=1011)thennext_stateif(keypressed=1and keyvalue=1011)thennext_state=count;elsif(keypressed=1and keyvalue=0101)thennext_state=modifytime4;time_temp(15 downto 12)=keyvalue;elsenext_state=present_state;time_temp=time_temp;end if;,when modifytime4=if(keypressed=1and keyvalue=1011)thennext_stateif(keypressed=1and keyvalue=1011)thennext_state=count;elsif(keypressed=1and keyvalue=0101)thennext_state=modifytime6;time_temp(7 downto 4)=keyvalue;elsenext_state=present_state;time_temp=time_temp;end if;,when modifytime6=if(keypressed=1and keyvalue=1011)thennext_stateif(keypressed=1and keyvalue=1011)thennext_state=count;elsif(keypressed=1and keyvalue=1010)thennext_state=loadtime;elsenext_state=present_state;end if;time_temp=time_temp;,when loadtime=next_stateif(keypressed=1and keyvalue=1011)thennext_state=count;elsif(keypressed=1and keyvalue=0010)thennext_state=setalarm2;time_temp(23 downto 20)=keyvalue;elsenext_state=present_state;time_temp=time_temp;end if;,when setalarm2=if(keypressed=1and keyvalue=1011)thennext_stateif(keypressed=1and keyvalue=1011)thennext_state=count;elsif(keypressed=1and keyvalue=0101)thennext_state=setalarm4;time_temp(15 downto 12)=keyvalue;elsenext_state=present_state;time_temp=time_temp;end if;,when setalarm4=if(keypressed=1and keyvalue=1011)thennext_stateif(keypressed=1and keyvalue=1011)thennext_state=count;elsif(keypressed=1and keyvalue=0101)thennext_state=setalarm6;time_temp(7 downto 4)=keyvalue;elsenext_state=present_state;time_temp=time_temp;end if;,when setalarm6=if(keypressed=1and keyvalue=1011)thennext_stateif(keypressed=1and keyvalue=1011)thennext_state=count;elsif(keypressed=1and keyvalue=1010)thennext_state=loadalarm;elsenext_state=present_state;end if;time_temp=time_temp;,when loadalarm=next_statenext_state=count;time_temp=time_temp;end case;end if;end process;buffertime=time_temp;,process(present_state)beginif(present_state=count)theniscount=1;elseiscount=0;end if;if(present_state=loadtime)thentimeload=1;elsetimeload=0;end if;if(present_state=loadalarm)thenalarmload=1;elsealarmload=0;end if;end process;end rt;,