【英文资料】16 BIT KOGGESTONE TREE ADDER.ppt

1,16 BIT KOGGE-STONE TREE ADDER,2,Agenda,AbstractIntroductionWhy Tree Adder?TheoryProject DetailsSummary of ResultsLessons LearnedCost AnalysisConclusion,3,Abstract,We designed 16 bit Kogge-Stone Tree Adder-the most commonly used parallel prefix carry-lookahead adder topology.200MHz clock frequencyArea 1000*600 um2Power density AMI06 Technology,4,Introduction,Why?-minimum logic depth,wide wiring channels,regular structure and large fanout points.Prefix Adder Structure,5,PROJECT DETAILS,17 pin outs 33 input D-flip flops and 17 output D-flip flopsCreate schematic and layout for 16 bit tree adderTest schematic using test benchRun DRC and LVS to verify the design,6,BLOCK DIAGRAM,7,Longest path calculation,Tphl=5ns/(14+3)=.29ns,8,Table of actual Wn&Wp,9,Schematic,10,Layout,11,DRC Report,12,Extraction report,13,LVS Report,14,Cost Analysis,Estimate amount of time spent on project:-Verifying NC Verilog5 hrs-Verifying Timing10 hrs-Layout40 hrs-Post Extracted Timing10 hrs,15,Lessons Learned,Start earlyWork in groupStudy previous projectsSeek advice from Dr.Parent and previous studentsSave time for debugging error,16,Conclusions,We designed and implemented a 16 bit Kogge-Stone Tree Adder that operates at 200MHz in an area of 1000*600 um2,17,Acknowledgements,Thanks to Cadence Design Systems for the VLSI labThanks to Dr.David ParentThanks to all 166,167,and 224 students,