静态时序分析基本原理和时序分析模型.ppt

Quartus II Software Design Series:Timing Analysis,-Timing analysis basics,2,Objectives,Display a complete understanding of timing analysis,3,How does timing verification work?,Every device path in design must be analyzed with respect to timing specifications/requirementsCatch timing-related errors faster and easier than gate-level simulation&board testingDesigner must enter timing requirements&exceptionsUsed to guide fitter during placement&routingUsed to compare against actual results,IN,CLK,OUT,combinational delays,CLR,4,Timing Analysis Basics,Launch vs.latch edgesSetup&hold timesData&clock arrival timeData required timeSetup&hold slack analysisI/O analysisRecovery&removalTiming models,5,Path&Analysis Types,Three types of Paths:Clock PathsData PathAsynchronous Paths*,Clock Paths,Async Path,Data Path,Async Path,Two types of Analysis:Synchronous clock&data pathsAsynchronous*clock&async paths,*Asynchronous refers to signals feeding the asynchronous control ports of the registers,6,Launch&Latch Edges,CLK,Launch Edge,Latch Edge,Data Valid,DATA,Launch Edge:the edge which“launches”the data from source registerLatch Edge:the edge which“latches”the data at destination register(with respect to the launch edge,selected by timing analyzer;typically 1 cycle),7,Setup&Hold,Setup:The minimum time data signal must be stableBEFORE clock edgeHold:The minimum time data signal must be stableAFTER clock edge,Valid,DATA,CLK,DATA,Together,the setup time and hold time form a Data Required Window,the time around a clock edge in which data must be stable.,8,Data Arrival Time,Data Arrival Time=launch edge+Tclk1+Tco+Tdata,CLK,Launch Edge,The time for data to arrive at destination registers D input,Comb.Logic,9,Clock Arrival Time,Clock Arrival Time=latch edge+Tclk2,CLK,Latch Edge,The time for clock to arrive at destination registers clock input,Comb.Logic,10,Data Required Time-Setup,Data Required Time=Clock Arrival Time-Tsu-Setup Uncertainty,CLK,Latch Edge,The minimum time required for the data to get latched into the destination register,Data must be valid here,Comb.Logic,11,Data Required Time-Hold,Data Required Time=Clock Arrival Time+Th+Hold Uncertainty,CLK,Latch Edge,The minimum time required for the data to get latched into the destination register,Data mustremain validto here,Comb.Logic,12,Setup Slack,The margin by which the setup timing requirement is met.It ensures launched data arrives in time to meet the latching requirement.,CLK,Launch Edge,Latch Edge,Comb.Logic,13,Setup Slack(contd),Positive slackTiming requirement metNegative slackTiming requirement not met,Setup Slack=Data Required Time Data Arrival Time,14,Hold Slack,The margin by which the hold timing requirement is met.It ensures latch data is not corrupted by data from another launch edge.,CLK,Latch Edge,Next Launch Edge,Comb.Logic,15,Hold Slack(contd),Positive slackTiming requirement metNegative slackTiming requirement not met,Hold Slack=Data Arrival Time Data Required Time,16,FPGA/CPLD or ASSP,ASSP or FPGA/CPLD,I/O Analysis,Analyzing I/O performance in a synchronous design uses the same slack equationsMust include external device&PCB timing parameters,CL*,Tdata,Tclk1,Tclk2,OSC,Data Arrival Path,Data Arrival Path,Data Required Path,*Represents delay due to capacitive loading,17,Recovery&Removal,Recovery:The minimum time an asynchronous signal mustbe stable BEFORE clock edgeRemoval:The minimum time an asynchronous signal mustbe stable AFTER clock edge,CLK,ASYNC,18,Asynchronous=Synchronous?,Asynchronous control signal source is assumed synchronousSlack equations still applydata arrival path=asynchronous control pathTsu Trec;Th TremExternal device&board timing parameters may be needed(Ex.1),ASSP,FPGA/CPLD,OSC,FPGA/CPLD,Example 1,Example 2,Data arrival path,Data arrival path,Data required path,Data required path,19,Why Are These Calculations Important?,Calculations are important when timing violations occurNeed to be able to understand cause of violationExample causesData path too longRequirement too short(incorrect analysis)Large clock skew signifying a gated clock,etc.TimeQuest timing analyzer uses themEquations to calculate slackTerminology(launch and latch edges,Data Arrival Path,Data Required Path,etc.)in timing reports,20,Timing Models in Detail,Quartus II software models device timing at two PVT conditions by defaultSlow Corner ModelIndicates slowest possible performance for any single pathTiming for slowest device at maximum operating temperature and VCCMINFast Corner ModelIndicates fastest possible performance for any single pathTiming for fastest device at minimum operating temperature and VCCMAXWhy two corner timing models?Ensure setup timing is met in slow modelEnsure hold timing is met in fast modelEssential for source synchronous interfacesThird model(slow,min.temp.)available only for 65 nm and smaller technology devices(temperature inversion phenomenon),21,Generating Fast/Slow Netlist,Specify one of the default timing models to be used when creating your netlistDefault is the slow timing netlistTo specify fast timing netlistUse-fast_model option with create_timing_netlist commandChoose Fast corner in GUI when executing Create Timing Netlist from Netlist menuCANNOT select fast corner from Tasks Pane,22,Specifying Operating Conditions,Perform timing analysis for different delay models without recreating the existing timing netlistTakes precedence over already generated netlistRequired for selecting slow,min.temp.model and other models(industrial,military,etc.)depending on deviceUse get_available_operating_conditions to see available conditions for target device,Reference Documents,Quartus II Handbook,Volume 3,Chapter 7 The Quartus II TimeQuest Timing AnalyzerQuick Start Tutorial Cookbook,Reference Documents,SDC and TimeQuest API Reference ManualAN 481:Applying Multicycle Exceptions in the TimeQuest Timing AnalyzerAN 433:Constraining and Analyzing Source-Synchronous Interfaces,25,Online TrainingWith Alteras online training courses,you can:Take a course at any time that is convenient for youTake a course from the comfort of your home or office(no need to travel as with instructor-led courses)Each online course will take approximate one to three hours to complete.,http:/trainingView training class schedule&register for a class,Learn More Through Technical Training,26,Altera Technical Support,Reference Quartus II software on-line help Quartus II HandbookConsult Altera applications(factory applications engineers)MySupport:http:/Hotline:(800)800-EPLD(7:00 a.m.-5:00 p.m.PST)Field applications engineers:contact your local Altera sales officeReceive literature by mail:(888)3-ALTERAFTP:World-wide web:http:/Use solutions to search for answers to technical problems View design examples,