可测性设计及DFT软件的使用.ppt
可测性设计及DFT软件的使用,张艳2007-11-5,20007-11-5,共49页,2,Outline,DFT基础DFTCompile生成扫描链TetraMAX生成ATPG设计实例,20007-11-5,共49页,3,DFT基础,测试DFT故障模型ATPGDFT常用方法,20007-11-5,共49页,4,测试(1-3),CMOS反相器中的物理缺陷,20007-11-5,共49页,5,测试(2-3),目前的产品测试方法,20007-11-5,共49页,6,测试(3-3),ATE,20007-11-5,共49页,7,DFT基础,测试DFT故障模型ATPGDFT常用方法,20007-11-5,共49页,8,DFT(Design For Test),controllabilityobservability,20007-11-5,共49页,9,DFT基础,测试DFT故障模型ATPGDFT常用方法,20007-11-5,共49页,10,故障模型,物理故障逻辑故障封装引脚间的漏电或短路 单一固定故障芯片焊接点到管脚连线断裂延时故障表面玷污、含湿气静态电流故障金属层迁移、应力、脱皮 金属层开路、短路,20007-11-5,共49页,11,单一固定故障,20007-11-5,共49页,12,等价故障(1/3),20007-11-5,共49页,13,等价故障(2/3),20007-11-5,共49页,14,等价故障(3/3),NAND的输入SA0和输出的SA1效果等效,A SA0,B SA0,Y SA1是一个等效故障集,20007-11-5,共49页,15,故障压缩,20007-11-5,共49页,16,不可测故障,20007-11-5,共49页,17,DFT基础,测试DFT故障模型ATPGDFT常用方法,20007-11-5,共49页,18,ATPG,ATPG Automatic Test Pattern GeneratorD算法PODEM(Goel)FAN(Fujiwara和Shimono)高级算法,20007-11-5,共49页,19,D算法,20007-11-5,共49页,20,D算法-activate the SA0 fault,20007-11-5,共49页,21,D算法-propagate fault effect,20007-11-5,共49页,22,D算法-anatomy of a test pattern,20007-11-5,共49页,23,D算法-record the test pattern,20007-11-5,共49页,24,DFT基础,测试DFT故障模型ATPGDFT常用方法,20007-11-5,共49页,25,DFT常用方法,功能点测试 需在每个测试点增加可控的输入和输出，I/O增加扫描测试 结构化的DFT技术，全扫描和部分扫描内建自测试 消除了对ATE的存储能力和频率的限制，更具发展潜力,20007-11-5,共49页,26,扫描测试(1/2),20007-11-5,共49页,27,扫描测试(2/2),20007-11-5,共49页,28,Outline,DFT基础DFTCompile生成扫描链TetraMAX生成ATPG设计实例,20007-11-5,共49页,29,设计流程,20007-11-5,共49页,30,普通D触发器,20007-11-5,共49页,31,Test-Ready Compilation,set_scan_configuration-style multiplexed_flip_flop-clock_mixing no_mix-chain_count 1set_dft_signal-view existing_dft-type ScanClock-port clk-timing 1 8.5set_dft_signal-view existing_dft-type Reset-port rst_n-active_state 0set_dft_signal-view spec-type ScanEnable-port se-active_state 1set_dft_signal-view spec-type ScanDataIn-port aset_dft_signal-view existing_dft-type ScanDataOut-port o,20007-11-5,共49页,32,Test DRC,check_scan or check_test这两个命令检查以下四类可测性问题：模型问题，诸如是否缺少相应的扫描单元；拓扑结构问题，例如是否存在不受时钟控制的组合逻辑反馈回路；确定测试协议，如找出测试时钟端口，找出测试模式下固定电平的测试状态端口；测试协议仿真，检查扫描过程是否可以正确的进行。,20007-11-5,共49页,33,Preview Scan Architecture,preview_scan show all预览将要生成的扫描链的大致情况，及时发现不合乎要求的地方。,20007-11-5,共49页,34,Scan Insertion,insert_scan使扫描触发器串链，建立和排序扫描链，同时进行优化以去除违反的DRC规则。,20007-11-5,共49页,35,扫描触发器,20007-11-5,共49页,36,Report,report_constraint-all_violatorsreport_scan_path-view existing_dft-chain report_scan_path-view existing_dft-cell estimate_test_coverage,20007-11-5,共49页,37,Export to TetraMAX,write_test_protocol-output./report/add.spfwrite-f verilog-hie-output./report/add.v,20007-11-5,共49页,38,Outline,DFT基础DFTCompile生成扫描链TetraMAX生成ATPG设计实例,20007-11-5,共49页,39,设计流程,20007-11-5,共49页,40,Read the Netlist,BUILD read netlist mydesign.v读入DFTC转交给TetraMAX的网表文件。,20007-11-5,共49页,41,Read Library Models,BUILD read netlist library./simic18.v必须读入所有和你的设计相关的verilog库模型，此库文件由工艺厂商提供。,20007-11-5,共49页,42,Build the Model,BUILD run build_model top_module,20007-11-5,共49页,43,Performing DRC,BUILD run drc mydesign.spf 测试协议文件的DRC检查,20007-11-5,共49页,44,Preparing for ATPG,TEST add faults-all 初始化故障列表以产生一份新的在ATPG设计模型中包含所有可能的故障点的故障列表,20007-11-5,共49页,45,Run ATPG,TEST run atpg random 默认情况下，TetraMAX先执行Basic-Scan ATPG，接着是Sequential ATPG，最后是Full-Sequential ATPG,20007-11-5,共49页,46,Review Test Coverage,TEST report summariesTEST report patterns summary查看测试覆盖率和产生的矢量的数目，若测试覆盖率很低，则需要重新进行ATPG测试矢量生成，直到得到满意的测试覆盖率。,20007-11-5,共49页,47,Compress Test Patterns,TEST run pattern_compress 99 99指示按不同的顺序进行99次故障仿真,20007-11-5,共49页,48,Save Test Pattern,TEST write patterns patterns.stil-format stilTEST write faults faults.AU-class au.stil文件与.spf文件的格式一样，都是采用stil语言描述，所不同的是增加了pattern部分，给出了各个测试pattern的具体细节。,20007-11-5,共49页,49,Outline,DFT基础DFTCompile生成扫描链TetraMAX生成ATPG设计实例,
