《IC设计流程》PPT课件.ppt

2023/7/29,集成电路设计流程和EDA工具CAEDA EDA技术经理傅红军,2023/7/29,集成电路设计流程和EDA工具,Content of Presentation设计流程Functional VerificationSynthesisTimingTestingP&RPhysical Checking/ExtractionEDA Tools,2023/7/29,集成电路设计流程和EDA工具,Content of Presentation设计流程Functional VerificationSynthesisTimingTestingP&RPhysical Checking/ExtractionEDA Tools,2023/7/29,集成电路设计流程和EDA工具,设计流程两种设计流程自底向上(Bottom-up Approach）设计从basic cells，functional block，macro,到modules等等,如电路图输入设计自顶向下(Top-Down Approach)设计从高层次算法开始（在设计过程中往往采用综合工具）,2023/7/29,集成电路设计流程和EDA工具,设计流程自顶向下(Top-Down)的设计流程,Specification,RTL coding,FunctionalVerification,Synthesis&Optimizers,Place&Route,PhysicalVerification,Tape out,manufacturing,Packaging/Testing,2023/7/29,集成电路设计流程和EDA工具,Content of Presentation设计流程Functional VerificationSynthesisTimingTestingP&RPhysical Checking/ExtractionEDA Tools,2023/7/29,集成电路设计流程和EDA工具,Verification Methodologies动态仿真(Dynamic Simulation)用计算机仿真根据输入的激励来观察设计的输出结果的过程例子:SPICE；Verilog静态验证或分析(Static Verification or analysis)验证设计的等效性，确保设计性能满足设计要求;例子:形式验证（formal verification）静态时序分析（static timing analysis）,2023/7/29,集成电路设计流程和EDA工具,SimulationSoftware to simulate circuit behavior in virtual time(process events sequentially)Cover Behavior,RTL and gates levelPros:flexible easy debugging transparent,2023/7/29,集成电路设计流程和EDA工具,SimulationEvent-Driven SimulationCycle Base SimulationComplied Code Logic Simulation,2023/7/29,集成电路设计流程和EDA工具,Simulation AccelerationUse special hardware to simulate circuit behavior in virtual timeTraditionally only cover gate levelRTL technology is getting mature and well accepted,2023/7/29,集成电路设计流程和EDA工具,EmulatiomUse mirror hardware to mimic circuit behaviorDesigner are accepting emulationPros:for late design stage before tape out fast can connect to real time system prototyping,2023/7/29,集成电路设计流程和EDA工具,EmulatiomCons:more expensive difficult to use,timing users need it from early stage debugging,2023/7/29,集成电路设计流程和EDA工具,形式验证（Formal Verification）通过数学的方法证明不同层次设计的等效性；传统的验证方法：,2023/7/29,集成电路设计流程和EDA工具,形式验证（Formal Verification）形式验证方法：,spec,Designcreation,RTL,DesignImplementation,Gate,PhysicalImplementation,GDSII,形式验证（Formal Verification）形式验证方法：,EquivalenceChecker,EquivalenceChecker,2023/7/29,集成电路设计流程和EDA工具,Content of Presentation设计流程Functional VerificationSynthesisTimingTestingP&RPhysical Checking/ExtractionEDA Tools,2023/7/29,SystemLevelSynthesis,Synthesis OverviewTop-Down Design Flow,HighLevelSynthesis,RegisterLevelSynthesis,LogicLevelSynthesis,TechMapping,netlist,2023/7/29,集成电路设计流程和EDA工具,System Level SynthesisAt the highest of abstraction in the behavioral domainFunctionality(instruction set of computer)and a set of constraint to be met Speed,power consumption,fabrication cost are specified,2023/7/29,集成电路设计流程和EDA工具,High Level Synthesis“Behavioral description at the algorithmic level”The behavioral in terms of operation and computation sequences on inputs to produce the required outputs is specified,2023/7/29,集成电路设计流程和EDA工具,High Level SynthesisIn three areas:Resource Allocation:selects functional unit of appropriate types and number Scheduling:assigns the operation to time slots Resource Assignment:Assigns the operation to the specified functional units,2023/7/29,集成电路设计流程和EDA工具,Register Level SynthesisCycle-by-Cycle combinational behavior defined in programming language-like description;no structure Resynthesis:concerns the data path,resource allocation and assignment can be improved based on more detailed Knowledge about physical characteristcs of alernate implementation,2023/7/29,集成电路设计流程和EDA工具,Register Level Synthesis(cont.)Register Relocation:modifies the initial assignment of operation to control steps by structural changes Re-timing:optimizes the performanceHDL Synthesis:Correct translation of cycle-by-cycle behavior into functionally equivalent set of equations,2023/7/29,集成电路设计流程和EDA工具,Logic Level Synthesis(cont.)Logic level Synthesis The main point is optimization,logic-minimization Aiming the minimal area(measured as number of literals)Mapping Map the groups of abstract gates to matching physical library cells of a given target technology,2023/7/29,综合的具体过程,Synthesis=Translation+Optimization+Mapping,Residue0);If(high_bits=“10”)thenresidue0);End if;,Translation,Optimize+Map,GTECH:通用库,目标库,2023/7/29,综合的目的,提高效率,抽象,利用技巧,再利用,容易验证,容易移植,提高自身,2023/7/29,RTL综合的简单过程,2023/7/29,集成电路设计流程和EDA工具,Physical Synthesis物理综合=synthesis+placement+optimization在深亚微米设计中，考虑连线的延迟，加速时序收敛,2023/7/29,基于物理综合流程概述,RTL,Synthesis(DC),Floorplan(SE),Cell Placement(PC),CTGEN&Routing(SE),RC extraction(HyperExtract),Verification(back annotation),STA(PT),DRC&LVS(Dracula),Tape out,DC:Design CompilerPC:Physical CompilerSE:Silicon EnsemblePT:Prime Time,DRC:Design Rule CheckLVS:Layout Versus SchematicSTA:Static Timing Analysis,2023/7/29,集成电路设计流程和EDA工具,Content of Presentation设计流程Functional VerificationSynthesisTimingTestingP&RPhysical Checking/ExtractionEDA Tools,2023/7/29,集成电路设计流程和EDA工具,Static Timing AnalysisA method for determining if a circuit meets timing constraints without having to simulate clock cycles Designs are broken down into sets of timing paths The delay of each path is calculated All path delays are checked to see if timing constraints have been meet,2023/7/29,集成电路设计流程和EDA工具,Static Timing VerificationTo check the potential timing violation setup time hold time pulse width clock skew checking etc.,2023/7/29,集成电路设计流程和EDA工具,Content of Presentation设计流程Functional VerificationSynthesisTimingTestingP&RPhysical Checking/ExtractionEDA Tools,2023/7/29,VLSI Realization Process,Determine requirements,Write specifications,Design synthesis and Verification,Fabrication,Manufacturing test,Chips to customer,Customers need,Test development,2023/7/29,Verification vs.Test,Verifies correctness of design.Performed by simulation,hardware emulation,or formal methods.Performed once prior to manufacturing.Responsible for quality of design.,Verifies correctness of manufactured hardware.Two-part process:1.Test generation:software process executed once during design2.Test application:electrical tests applied to hardwareTest application performed on every manufactured device.Responsible for quality of devices.,2023/7/29,DFT(Design-for-Test),Scan stuck-at/DC Delay/ACLogic BIST(Built-in Self-Test)Memory BIST iddq,2023/7/29,Scan path扫描路径法,扫描路径法是一种规则的可测试性设计方法，适用于时序电路。其设计思想是把电路中的关键节点连接到一个移位寄存器上，当作为扫描路径的移位寄存器处于串入/并出状态时，可以用来预置电路的状态。当作为扫描路径的移位寄存器处于并入/串出状态时，可以把内部节点的状态依次移出寄存器链。,2023/7/29,集成电路设计流程和EDA工具,Content of Presentation设计流程Functional VerificationSynthesisTimingTestingP&RPhysical Checking/ExtractionEDA,2023/7/29,集成电路设计流程和EDA工具,Content of Presentation设计流程Functional VerificationSynthesisTimingTestingP&RPhysical Checking/ExtractionEDA Tools,2023/7/29,集成电路设计流程和EDA工具,Physical CheckingDesign Checks Performed After P&R Before Fabrication Related to Spacing,Connections,ViasElectrical Checks Performed During P&R Focus on Short Circuit,Open Circuit and Floating NodesLVS Performed After P&R To Ensure Final Physical Layout Is consistent To Input Netlist,2023/7/29,Circuit Extraction,Convert layout geometry to circuit netlistdevicessometimes convert to gatesconnectivityparasiticsGoalverify that layout matches circuitassume layout passes DRCdetermine actual circuit parasiticsback-annotate and resimulateuse minimum CPU time,memoryintegrated extractor+layout editoruse existing data structuresextract interactively,2023/7/29,EDA tools,2023/7/29,Respondents use EDA tools for a variety of functions,2023/7/29,Cadence and Synopsys tools are currently most used,2002,2023/7/29,About CAEDA,CAEDA 致力于为科研,企业,教育等部门提供国际上最新、最先进的EDA设计，以及集成电路设计咨询和解决方案 CAEDA 业务包括三个方面:设计咨询服务 ConsultancyEDA和CAE销售 CAE/EDA software distribution培训课程 Training courses,2023/7/29,CAEDA EDA 产品介绍,ADiT数模混合电路级仿真解决方案DesignCraft 逻辑综合工具DesignCraft Pro 物理综合工具TimeCraft静态时序分析工具Laker全定制版图工具DebussyHDL调试工具Specmant Elite自动化系统功能验证工具,2023/7/29,SPICEINPUT DECK,Verilog(HDL),Parser&Partition,MOSFET Table,Debussy(nWave),ADiT-PLOT,ADiT-Engine,SPICE,Turbo,MOT,HDL,Veritools(undertow),VPI,ADiTAnalog,Digital Turbo Simulator,2023/7/29,Laker L3full custom IC design,Design browser Easily traverse designManipulate logic hierarchy to optimize for layout purposeD&D devices to create layoutSchematic generatorForm-gate and user defined symbols make it more readable than CDL netlistHelp layout planning Layout windowFlight lines to show the connectivityReal-time short detectorCross probing,2023/7/29,Verification=Detection+Debug,ChangeCode,SimulateAgain,Capture,Intent,Detect,Errors,Debug,Capture,Design,Verilog,VHDL,Testbench,Verification Process,Modify design,Understand design,Locate/isolatecauses&effects,Verification,Understand design,Debug Process,Debussy HDL debugging solution,2023/7/29,TimeCraft Design Flow,Place&Route,Constraints,Synthesis,Libraries,RTL,Netlist,IncentiaTimeCraft,Pre-layout,Analysis,Post-layout,Analysis,Sign-off,(Synopsys.lib),(Synopsys SDC),RC Extraction,SDFDSPF/SPEF,TimeCraft fast STA solution,2023/7/29,Design Craft/pro synthesis solution,DesignCraftLogic Synthesis,Netlist,DesignCraft ProPhysical Synthesis,Placed Gates,RTL,RTL,Netlist(Post-synthesis),Placed Gates(Post-placement),DFT OptionLow Power Option,Physical Synthesis,2023/7/29,Verisity 自动化验证解决方案,e Language 验证语言；,2023/7/29,谢谢！欢迎访问我们的网站：,