数字逻辑第三章,英文.ppt
1,Chapter 4,Combinational Logic Design Principles,2,Preface,Combinational Logic Circuit,Sequential Logic Circuit,Combinational Logic Circuit,Input,Output,Logic Gates,Input,Output,Feedback Logic,Sequential Logic Circuit,3,Design Step,Emphasis,4,4.1 Switching Algebra,Boolean Algebra(1854),1.Axioms,Positive-Logic,Negative-Logic,1-High 0-Low,0-High 1-Low,Default as Positive-Logic,George Boole1815-1864,5,(A1),(A2),(A3),(A4),(A5),6,2.Theorems,(T1),Identities,(T2),Null elements,(T3),Idempotency,(T4),Involution,(T5),Complements,Single-Variable Theorems,7,(T6),Commutativity,(T7),Associativity,(T8),Distributivity,(T9),Combining,8,(T10),Covering,(T11),Consensus,(T12),DeMorgans,9,Prove by using Truth Table,X,Y,0 0,0 1,1 0,1 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,(T13),Extending 1,Augustus De Morgan1806-1871,10,3.Rules,I.Replacing,Ex.4-1,If,then,n-Variable DeMorgans theorems,11,II.Shannons Expansion,Claude Elwood Shannon1916-2001,1937,Prove?,12,III.Inversion,whole,Be known,Ask for,Principle of Inversion:,Swapping“+”and“”.,Swapping“1”and“0”.,Complementing all Uncomplemented variables,and Uncomplementing all Complemented ones.,Ex.4-2,Retain of original Sequence ofOperation,First“”and Secend“+”,(,),(,),Or,13,IV.Duality,Positive Logic,Negative Logic,Principle of Duality:,Swapping“+”and“”.,Swapping“1”and“0”.,Retain of original Sequence ofOperation,Ex.4-3,Distributivity,14,4.Standard Representations of Logic Functions,Sum of products,AND-OR,Product of sums,OR-AND,NAND-NAND,NOR-NOR,AND-OR-NOT,Base Rpresentations,15,5.Minterm and Maxterm,An n-variable minterm is a normal product term with n literals.,An n-variable maxterm is a normal sum term with n literals.,2n such product terms.,2n such sum terms.,mi,i=0,1,2n-1,Mi,i=0,1,2n-1,16,Ex.4-4,3-variablesA,B,C,23(8)minterms,A B C,0 0 0,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,m0,m1,m2,m3,m4,m5,m6,m7,Every minterm is exclusive.,if,17,Ex.4-5,3-variablesA,B,C,23(8)maxterms,A B C,0 0 0,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,0,1,1,1,1,0,1,1,1,1,1,0,1,1,1,0,1,1,1,1,0,1,1,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,M7,M6,M5,M4,M3,M2,M1,M0,Every maxterm is exclusive.,if,Relationship between minterms and maxterms:,18,Ex.4-6,A B C,0 0 0,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,F,0,1,0,1,0,0,1,1,m1,m3,m6,m7,“0”,“1”,“0”,“1”,Maxterm,Minterm,M0,M2,M4,M5,F,1,0,1,0,1,1,0,0,m0,m2,m4,m5,19,4.2 Combinational Circuit Analysis,A,B,C,F,A,B,C,B,B,A,C,C,Behave of the circuit.,Get different circuit structure.,3 Invertors,4 AND Gates,3 OR Gates,20,AND-OR,OR-AND,1 Invertor,2 AND Gates,1 OR Gate,1 Invertor,1 AND Gate,2 OR Gates,NAND-NAND,1 Invertor,3 NAND Gates,NOR-NOR,1 Invertor,3 NOR Gates,Faster,Faster,21,AND-OR,A,B,C,F,De Morgan Theorems:,NAND-NAND,HOMEWORK:P2314.9 4.14(Using Theorems),22,4.3 Combination-Circuit Synthesis,Design Step,23,Ex.4-7,Design a circuit for vote.One manager,and two clerks.,If the manager dissents,then the proposal isnt passed.If the manager agrees,and any other clerk agrees too,then the proposal is passed.,Assume:manager is A,clerks are B and C.,agreeing-1,and disagreeing-0,passing-1,and not passing-0,A B C,0 0 0,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,F,0,0,0,0,0,1,1,1,Ouput is F.,AND-OR,NAND-NAND,24,Combinational-Circuit Minimization,Minimizing the number of first-level gate.,Minimizing the number of inputs on each first-level gate.,Minimizing the number of inputs on the second-level gate.,Inputs on first-level gate,First-level gate,25,1.Minimization using Boolean Theorems,Combining,Covering,Consensus,Extending 1,26,2.Karnaugh Maps,Maurice Karnaugh,1953,Truth Figure,m0,m1,m2,m3,0,1,0,1,0,1,00,01,11,10,m0,m1,m3,m2,m4,m5,m7,m6,00,00,01,01,11,11,10,10,m4,m1,m3,m2,m0,m5,m7,m6,m12,m13,m15,m14,m8,m9,m11,m10,2-variables,3-variables,4-variables,Gray Codes,For usingCombining!,1951,Edward W Veitch,27,Using Method of Karnaugh Maps,Covering Logic Adjacent 1-cells,Only one variable is different.,For Using Combination Theorem.,Logic Adjacent 1-cells:,Immediately adjacent,Wraparound,Symmetrical,Covering Principles:,Each circle covers has 2i 1-cells.,Range of each circle covers is the largest possible.,Quantity of circle covers is the least possible.,Each circle covers has one 1-cell different from others at least.,Remove i-variables from product term.,28,Ex.4-8,Simplifying,00,00,01,01,11,11,10,10,Truth Table,A B C D,0 0 0 0,0 0 0 1,0 0 1 0,0 0 1 1,0 1 0 0,0 1 0 1,0 1 1 0,0 1 1 1,1 0 0 0,1 0 0 1,1 0 1 0,1 0 1 1,1 1 0 0,1 1 0 1,1 1 1 0,1 1 1 1,F,1,1,0,0,1,0,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,Distinguished 1-cell,1,1,1,1,1,1,“0”,“1”,Sum of products,29,00,00,01,01,11,11,10,10,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,“0”,“1”,Product of sums,Distinguished 0-cell,30,“Dont care”Input Combinations,Inhibiting term,Optional term,BCD(8421)10101111,Turn clockwise,if A=1Turn anticlockwise,if B=1Stop,if C=1,A,B and C are inhibiting variables,Ex.4-9,Inhibiting terms:,31,00,00,01,01,11,11,10,10,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,00,00,01,01,11,11,10,10,0,d,0,d,d,d,0,0,0,1,1,1,1,1,1,1,Not using Inhibiting terms,Using Inhibiting terms,HOMEWORK:P2314.14,4.18,4.55,4.59,32,4.4 Timing Hazards,While,At the same time,0-glitch,Static-1 hazard,If,1-glitch,Static-0 hazard,33,Find the conditions for,(Sum of products),(Product of sums),0,1,00,01,11,10,0,0,0,0,1,1,1,1,Tangency,Consensus term,Circuit with static-1 hazard eliminated,HOMEWORK:P232 4.19,
