数字设计课件第六章组合逻辑设计实践.ppt
2023/5/29,1,Chapter 6 Combinational Logic Design Practices,MSI building blocks are the important element of combinational circuits.,2023/5/29,chapter 6,2,本章重点,具备一定功能的通用组合逻辑电路的设计方法及实例掌握常用的MSI的使用方法及功能扩展掌握译码器、MUX实现组合逻辑功能的方法能分析、设计由MSI构建的电路,2023/5/29,chapter 6,3,6.1 Documentation Standard,1.Signal Names and Active LevelsMost signals(signal name)have active level.active high active lowNaming convention surffix“_L”attaching to signal name represent active low level.Like,EN_L、READY_L In logic relation,EN_L=EN，READY_L=READY。,2023/5/29,chapter 6,4,2.Active levels for pins,2023/5/29,chapter 6,5,Exp2：EN=1(active high),data can be transferredEN=0(active low),data can be transferred,EN,CLK,2023/5/29,chapter 6,6,3.bubble-to-bubble logic design,Make the logic circuit easier to understand.Exp：,2023/5/29,chapter 6,7,6.3 Combinational PLDs,1.Programmable logic arrays(PLA)two level“ANDOR”device.Can be programmed to realize any sum-of-products logic expression.An nm PLA with p product terms:ninputs moutputs pproduct terms,2023/5/29,chapter 6,8,43 with 6 product terms,AND array,OR array,2023/5/29,chapter 6,9,2023/5/29,chapter 6,10,2.Programmable Array Logic Devices,Fixed OR array，programmable AND arrayBidirectional input/output pins，熔丝型PAL16L8，,Output enable,2023/5/29,chapter 6,11,3.Generic Array Logic Devices（GAL）,an innovation of the PAL;can be erased and reprogrammed;,2023/5/29,chapter 6,12,6.4 Decoder,An important type of combinational circuit.,Output code word,decodeer,1-to-1mapping,1-out-of-m code,nm,n-bit,m-bit,2023/5/29,chapter 6,13,1、bianry decoders,input code：n-bitoutput code：2n-bit 2-4 decoder（2-22）,I1,I0,Y3,Y2,Y1,Y0,truth table：？,Yi：？,Yi=miY0=I1I0Y1=I1I0Y2=I1I0Y3=I1I0,2-4decoder,One input combination chooses an output port.,2023/5/29,chapter 6,14,2-4 decoder with enable inputYi=EN mi,2023/5/29,chapter 6,15,（2）74139,dual 2-4 decoder,Input code：B（MSB）A（LSB）Also be called address input.Output code：Y3_LY0_L,2023/5/29,chapter 6,16,（3）74138,3-8 decoder,Enable inputEN=G1G2A_LG2B_LInput code：C（MSB）、B、AOutput code：Y0_L Y7_LYi_L=（ENmi）,2023/5/29,chapter 6,17,2023/5/29,chapter 6,18,2、realizing combinational circuits with decoder,review：canonical sumDecoder output：Yi_L=(ENmi)when EN=1，Yi_L=mi=Mi add an NAND gate to the decoders output.Exp:(1)F=AB（0、3）,F=AB+AB,2023/5/29,chapter 6,19,（2）if a 3-bit number XYZ is odd number，then ODD output 1，else output 0.realize the function with decoder and gates.solution：F=？F=XYZ（1，3，5，7）,2023/5/29,chapter 6,20,（3）F=XYZ（0、1、5）解：,2023/5/29,chapter 6,21,3.Cascading binary decoders,How to construct a 4-16、5-32 decoder？use multiple 2-4 or 3-8 decoders to cascade.PS.：confirm the number of decoders according to the input and output bits.only one chip works in each decoding.,2023/5/29,chapter 6,22,Exp：a 4-16 decoder,Inputs:4-bit N3、N2、N1、N0。Outputs:16-bit DEC15_LDEC0_LNeed 2 3-8 decoders.Use the MSB of the inputs as chip-select bit.,N3 N2 N1 N0,N3 N2 N1 N0,2023/5/29,chapter 6,23,Chip selecting,2023/5/29,chapter 6,24,Exp：4-bit prime-number detector.Realizing it with 74138 and some gates.,N3,N2,N1,N0,F,2023/5/29,chapter 6,25,4、7-segment decoder,Classify of 7-seg displayer：in materials:LED（发光二极管）LCD（液晶）In working mode:common-cathode(共阴极)common-anode(共阳极),2023/5/29,chapter 6,26,7-segment decoder transform the input BCD code to 7-segment displaying code.devices：7446A、74LS47（驱动共阳）74LS48、74LS49（驱动共阴）,00001001 are useful input codes.10101111 are unused BCD code.,2023/5/29,chapter 6,27,74LS49,2023/5/29,chapter 6,28,5、BCD decoder（二十进制译码器）,Inputs:BCD,Y0,Y9,BCD decoder,Output:1-out-of 10 code,2023/5/29,chapter 6,29,5.5 Encoder,1、binary encoder,inputs:,1-out-of-2n code,I0,I1,Im,(m=2n-1),output:,n-bit,Y0,Y1,Yn-1,binary encoder,2023/5/29,chapter 6,30,8-3 encoder,In/out:active high,2023/5/29,chapter 6,31,Y0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I7,2023/5/29,chapter 6,32,2、Priority Encoder,if multiple inputs are asserted,how to deal with?solution：assign priority to each input from high to low.let I7 highest priority and decrease from I6 down to I0 A2,A1,A0encode output IDLEwhen no input is asserted,IDLE=1,2023/5/29,chapter 6,33,2023/5/29,chapter 6,34,2023/5/29,chapter 6,35,3、74148 Priority Encoder,EI_L：Enable Input.I7_LI0_L：encode input，I7_L has highest priority.A2_LA0_L：encode outputGS_L：GS_L=0 when one or more of the request inputs are asserted.EO_L：enable output,EO_L=0 when all of the request inputs are negative and EI_L=0.,2023/5/29,chapter 6,36,74148真值表,2023/5/29,chapter 6,37,4、cascading priority encoder,problem：how to construct 16-4、32-5 priority encoder？Connecting multiple 8-3 endoder.note：make sure the needed number of chips according to the inputs.need to redesign the output circuit that could produce the correct encoding output.,2023/5/29,chapter 6,38,16-4 priority encoder:use two 74148 U1、U2，U1:input E15_LE8_L;U2:input E7_LE0_L;E15_L is the highest priority,output:A3A0，active high;When one or more inputs is asserted，GS0=1；and A3A0=0000。,U1,U2,2023/5/29,chapter 6,39,思考：若需要编码输出、GS0为低电平有效，如何修改电路输出结构？P.413 figure 6-49 shows the 32-5 priority encoders strcture,.,2023/5/29,chapter 6,40,6.6 Three-state Devices,1、three-state buffers,2023/5/29,chapter 6,41,EN_L,A,OUT,EN,EN_L,A,A,OUT_L,OUT_L,Enable means:the buffer output normal logic 0、1 when EN is asserted；the buffer output Hi-Z when EN is negated.,2023/5/29,chapter 6,42,Application,data,返回时序,address of data source,2023/5/29,chapter 6,43,Issues in application TPLZ、TPHZ：time that takes from normal logic into Hi-Z;TPZL、TPZH：time that takes from Hi-Z into normal logic;generally，TPLZ、TPHZ TPZL、TPZH But to confirm the correction in application,a control logic is adopted.,2023/5/29,chapter 6,44,74138的相关引脚信号,查看电路,截止时间（停滞时间）,2023/5/29,chapter 6,45,课堂练习,试设计一个电路，当控制信号M=1时，电路为“判一致”电路，即当三个输入变量取值全部相同时输入为1；当控制信号M=0时，电路为“多数表决”电路，即输出等于输入变量中占多数的取值。请写出最简表达式。（注：至少要写出卡诺图，三变量为X、Y、Z）,2023/5/29,chapter 6,46,6.7 Multiplexer,A,B,SEL,Y=A or B,2-to-1 MUX,Y=SELA+SELB,2023/5/29,chapter 6,47,又称数据选择器，简称MUXOutput:,enable,select,n data source,data output,n2s,mj：SELj minterm,1、基本结构：,2023/5/29,chapter 6,48,Let b=1,D0,D1,Dj,Dn-1,SEL,EN,Y,2023/5/29,chapter 6,49,Exp:4-to-1 MUX,2023/5/29,chapter 6,50,2、MSI MUX,（1）8-to-1 MUX，74151,EN_L,address,Y_L,Y,2023/5/29,chapter 6,51,返回,2023/5/29,chapter 6,52,（2）4-bit,2 input MUX，74157,2023/5/29,chapter 6,53,（3）2 bit,4 input MUX，74 153,1G_L,2G_L,2023/5/29,chapter 6,54,3、Expanding MUXs,Exp1：use 74151 to realize a 16-to-1 MUX,some gates can be used if necessary.Chips needed：according to the 16 inputs,2 74151 chips.output：combine two chips outputs into one output.,2023/5/29,chapter 6,55,The MSB(A3)of input act as the chip-select bit.,2023/5/29,chapter 6,56,Exp2：用74153实现4输入，4位MUX，。设4路输入分别是：1D3.0、2D3.0、3D3.0、4D3.0；4位输出是：Dout3.0 输入选择：S1、S0解：无需外加门，只需要合理安排输入、输出数据端口即可。,2023/5/29,chapter 6,57,S1S0,2023/5/29,chapter 6,58,4、用MUX实现组合逻辑函数的标准和,multiple input,1 bit MUX,the output：when EN is asserted：the canonical sum form.,74151的内部电路,2023/5/29,chapter 6,59,MUX的数据输入端与真值表的每行输出对应，MUX的地址选择端作为最小项产生器，即 真值表：输出值输入变量 MUX：数据输入端地址端例1：试设计一个数据检测电路，当输入3位二进制数能被3整除时，输出F为1，否则为0。请用74151实现该逻辑函数。解：F=XYZ（？）电路？,按最小项编号顺序,变量与选择端对应,2023/5/29,chapter 6,60,例1的电路,X,Y,Z,F,2023/5/29,chapter 6,61,例2：若例1中输入数为4位二进制数，如何实现？解1：用16输入，1位的MUX来实现，选用74150。F=WXYZ（0，3，6，9，12，15）解2：仍选用74151，先对所求函数的卡诺图做降维处理。预备知识：卡诺图的降维 用一个n变量的卡诺图来处理m变量的函数（nm），这种卡诺图被称为降维（降次）的卡诺图。它允许单元格中除了0、1、无关项外，还可包含单变量或逻辑表达式。,2023/5/29,chapter 6,62,卡诺图的降维,卡诺图降次的过程：设m=n+1，在m-变量函数F(X1,X2,Xn,Xn+1)中选择一个“入图”的变量Xi，用剩下的n个变量构造n-变量卡诺图。原图中变量Xi取值相反所覆盖的相邻的两个单元格被合并。（这两个单元格的其余变量是相同的；在真值表中对应着两行，只有Xi是不同的，其余变量均相同。）,00,01,11,10,F,W X,Y Z,00,01,11,W,Y,Z,X,10,2023/5/29,chapter 6,63,降维的基本步骤,先建新的真值表，表中的输入变量是除Xi而外剩下的变量，新行号由他们的组合值（最小项）确定。若在原(n+1)变量真值表中，被合并的两行的入图变量Xi与对应的F取值相同，则新表中F=Xi,2023/5/29,chapter 6,64,若在原(n+1)变量真值表中，被合并的两行的入图变量Xi与对应的F取值相反，则新表中F=Xi若在原(n+1)变量真值表中，被合并的两行的入图变量Xi所对应的F=1，则新表中F=1若在原(n+1)变量真值表中，被合并的两行的入图变量Xi所对应的F=0，则新表中F=0得新的n变量卡诺图用MUX实现,2023/5/29,chapter 6,65,2023/5/29,chapter 6,66,卡诺图中降维,原4变量卡诺图新3变量卡诺图,00,01,11,10,F,W X,Y Z,00,01,11,W,Y,Z,X,10,2023/5/29,chapter 6,67,例2的电路图,Z,Z,W,X,Y,F,2023/5/29,chapter 6,68,5.Multiplexers、Demultiplexers and Buses,demultiplexers,Din,2n bit parallel output,demultiplexers,1-bit,D0,D1,Dm,最多m=2n,No DeMUX chips,a binary decoder with enable input can be used as a DeMUX.,2023/5/29,chapter 6,69,MUX、DeMUX应用于数据的选择与分配,MUX：combine m parallel-input data sources into serial output data.DeMUX：route the bus data to 1 of m destinations.,2023/5/29,chapter 6,70,（1）MUX：parallel serial conversion,t,2023/5/29,chapter 6,71,2023/5/29,chapter 6,72,（2）DeMUX:serial parallel conversionUse a 74138 as a DeMUX.,2023/5/29,chapter 6,73,Diagram of Exp.,S2S1S0,111,110,101,100,011,010,001,000,0,1,0,1,0,1,0,1,2023/5/29,chapter 6,74,6.8 Exclusive-OR gates and Parity circuits,1、XOR and XNOR gates,（XY）,XOR,XNOR,记忆：异或门相同为0，相异为1 异或非门与异或相反,2023/5/29,chapter 6,75,Properties,X0=X X1=XXX=0 XX=1XY=Y X XYZ=(XY)Z=X(YZ)Equivalent symbols Any two signals(inputs or outputs)of an XOR or XNOR gate may be complemented without changing the resulting logic function.,2023/5/29,chapter 6,76,Feature of XOR expression(k-map),XYZ=XYZ+XYZ+XYZ+XYZ,010,100,001,111,XYZ,2023/5/29,chapter 6,77,2、parity circuits,n个异或门级联起来，可对n+1个数作奇校验（Odd-parity checking）。输入数中有奇数个1，则输出ODD=1。ODD=I1I2In,Daisy-chain connection,2023/5/29,chapter 6,78,Complement the output of odd-parity circuit，it can works as an Even-parity which output 1 if an even number of its input are 1.,Tree structure，has faster operation speed.,2023/5/29,chapter 6,79,奇偶校验的实现,奇偶校验码(补充)由n位信息位+1位奇偶校验位构成。偶校验编码：n+1位编码中包含偶数个1。奇校验编码：n+1位编码中包含奇数个1。例：某检测电路采用1位奇校验码方式，假设数据是三位，请给出奇偶校验位的产生电路。,输入,输出,2023/5/29,chapter 6,80,3、74280 9-bit parity generator,可在存储和发送码字时生成奇偶校验位，也可在恢复和接收码字时检查奇偶校验位。,EVEN=ABCDEF(GHI),ODD=ABCDEFGHI,2023/5/29,chapter 6,81,数据锁存,data,PIN,存储器,WR,RD,RD,WR,POUT,ERROR,0,1,0,1,ODD=ABCDEFGHI,=PIN=POUT,2023/5/29,chapter 6,82,5.9 比较器（Comparators）,比较器：比较器只比较两个数是否相等数值比较器将输入数解释为无符号数或符号数，并指出它们之间的算术关系（大于、等于、小于）。,2023/5/29,chapter 6,83,1、比较器结构,（1）1-bit比较器（2）多位比较器 并行比较 串行比较,DIFF=A0B0,EQ=（A0B0）,2023/5/29,chapter 6,84,并行比较器,4-bit 比较器,串行比较器：利用迭代电路,2023/5/29,chapter 6,85,2.迭代电路（Iterative Circuit）,迭代电路：由n个相同的模块电路串联而成，包含主输入、输出和级联输入、输出。,边界输出,2023/5/29,chapter 6,86,比较器模块迭代比较电路,速度慢，扩展方便,2023/5/29,chapter 6,87,3.数值比较器,（1）1-bit数值比较器（Magnitude comparators）,FAB=AB,FAB=AB,FA=B=AB+AB,2023/5/29,chapter 6,88,（2）多位数值比较器2-bit 数值比较器，输入数为A1.0、B1.0,从高位到低位逐位比较,2023/5/29,chapter 6,89,FAB=(A1B1)+(A1=B1)(A0B0)=A1B1+(AB+AB)(A1B1)FA=B=(A1=B1)(A0=B0)FAB=(A1B1)+(A1=B1)(A0B0),伪逻辑,2023/5/29,chapter 6,90,4.标准MSI比较器,4-bit 数值比较器7485级联输入：ALBI、AEBI、AGBI，用于比较器的扩展比较输出（级联输出）：ALBO、AEBO、AGBOAGBO=(AB)+(A=B)AGBIAEBO=(A=B)AEBIALBO=(AB)+(A=B)ALBI,2023/5/29,chapter 6,91,数值比较器的扩展 串行方式扩展,FAB,FA=B,FAB,2023/5/29,chapter 6,92,并行方式扩展,FAB,FA=B,FAB,X11.8,Y11.8,X7.4,Y7.4,X3.0,Y3.0,2023/5/29,chapter 6,93,5.10 加法器、减法器和ALU（Adders、Subtractors and ALU）,主要内容：二进制补码加/减法的电路实现1、1-bit半加器和全加器（1）半加器,半加和：HS=XY,进位输出：CO=XY,2023/5/29,chapter 6,94,（2）全加器,全加和：S=XYCIN,进位输出：CO=XY+CINX+CINY,2023/5/29,chapter 6,95,2、串行进位加法器,将1-bit全加器作为模块电路，可构成n-bit迭代型串行加法器。,电路简单，扩展方便，但运算速度慢,2023/5/29,chapter 6,96,3、超前进位加法器,是并行加法器问题：进位的信息传递解决：先行进位 利用算法用加数和被加数产生每位的 进位，而与低位的进位无关。（1）定义：进位产生变量：gi=xiyi 进位传递变量：pi=xi+yi 第i级的进位：Ci+1=gi+piCi,2023/5/29,chapter 6,97,Ci+1=gi+pi(gi-1+pi-1(g0+p0C0)C0=0，进位只与加数和被加数有关，可并行产生。Ci+1与三级电路对应，运算速度提高。（2）结构 和：Si=XiYiCi 进位：Ci+1=gi+piCi,两级与或式,2023/5/29,chapter 6,98,（3）MSI加法器74283，4-bit 超前进位加法器加法器的级联（P.310图5-92）,2023/5/29,chapter 6,99,4、减法器,全减器D=XYBINBO=BINY+BINX+XY,2023/5/29,chapter 6,100,二进制补码数（无符号数）的减法可以用加法来实现 X-Y=X+(Y)补=X+(Y)反+1新的表达式：D=XYBIN BO=(BINX+BINY+XY),全加器实现1-bit数的减法,D,BIN,BO,减法器,2023/5/29,chapter 6,101,5、MSI算术逻辑单元,可对2个b位操作数进行多种算术和逻辑操作。,ALU,A,B,F,SEL,M,CIN,CO,G,P,A=B,
