电子技术基础数字部分.doc

4.6.1module_2to4decoder(A1,A0,E,Y);input A,B,E;output 3:0Y;wire A1not,A0not,Enot;not n1(A1not,A1), n2(A0not,A0), n3(Enot,E);nand n4(Y0,A1not,A0not,Enot),n5(Y1,A1not,A0,Enot),n6(Y2,A1,A0not,Enot),n7(Y3,A1,A0,Enot);endmodule4.6.2module_2to1muxtri(A,B,SEL,L);input A,B,SEL; output L; tri L; bufif1(L,B,SEL); bufif0(L,A,SEL);endmodule4.6.3module halfadder(S,C,A,B); input A,B; output S,C;xor(S,A,B); and(C,A,B);endmodulemodule fulladder(S,CO,A,B,CI); input A,B,CI; output S,CO; wire S1,D1,D2;halfadder HA1(S1,D1,A,B); halfadder HA2(S,D2,S1,CI); or g1(CO,D2,D1);endmodulemodule_4bit_adder(S,C3,A,B,C_1); input3:0A,B; input C_1; output 3:0S; output 3:0C3; wire C0,C1,C2;fulladder FA0(S0,C0,A0,B0,C_1), FA1(S1,C1,A1,B1,C0), FA2(S2,C2,A2,B2,C1), FA3(S3,C3,A3,B3,C2);endmodule4.6.4module decoder_df(A1,A0,E,Y); input A1,A0,E; output3:0Y;assignY0=(A1&A0&E);assignY1=(A1&A0&E);assignY2=(A1&A0&E);assignY3=(A1&A0&E);endmodule4.6.5module binary_adder(A,B,Cin,SUM,Cout); input 3:0A,B; input Cin; output 3:0SUM; output Cout; assign Cout,SUM=A+B+Cin;endmodule4.6.6module mux2x1_df(A,B,SEL,L); input A,B,SEL; output L; assign L=SEL?A:B;endmodule4.6.7module mux2to1_bh(A,B,SEL,L); input A,B,SEL; output L; reg L; always (SEL or A or B) if(SEL=1) L=B; else L=A;endmodule4.6.8module mux4to1_bh(A ,SEL,E,L);input3:0A;input1:0SEL;output L;reg L;always (A or SEL or E) begin if(E=1) L=0;else case(SEL) 2 d0 :L=A0; 2 d1 :L=A1; 2 d2 :L=A2; 2 d3 :L=A3; endcase endendmodule5.5.1module D_lanch(Q,D,E); output Q; input D,E;reg Q;always (E or D) if(E) Q<=D;endmodule5.5.2module DFF(Q,D,CP);output Q; input D,CP; reg Q;always (posedge CP) Q<=D;endmodulemodule async_set_rst_DFF(Q,QN,D,CP,Sd,Rd);output Q,QN;input D,CP,Sd,Rd; reg Q,QN;always (posedge CP or negedge Sd or negedge Rd )if(Sd|Rd)if(Sd) begin Q<=1 b1; QN<=1 b0; end else begin Q<=1 b0; QN<=1 b1; endelse begin Q<=D; QN<=D; endendmodulemodule sync _rst_DFF(Q ,D,CP,Rd); output Q; input D,CP,Rd; reg Q; always (posedge CP) if(Rd)Q<=1 b0; else Q<=D;endmodule5.5.3module JK_FF(Q,Qnot,J,K,CP); output Q,Qnot; input J,K,CP; reg Q; assign Qnot=Q; always (negedge CP ) case (J,K) 2b00:Q<=Q;2b01:Q<=1b0;2b10:Q<=1b1;2b11:Q<=Q; endcaseendmodule6.6.1module shift74x194(S1,S0,D,Dsl,Dsr,Q,CP,CR); input S1,S0; input Dsl,Dsr; input CP,CR;input 3:0D;output 3:0Q;reg 3:0Q;always (posedge CP or negedge CR) if(CR)Q<=4b0000; else case(S1,S0) 2b00:Q<=Q; 2b01:Q<=Q2:0,Dsr; 2b10:Q<=Dsl ,Q3:1 ; 2b11:Q<=D; endcaseendmodule6.6.2module counter74x161(CEP,CET,PE,D,CP,CR,Q,TC); input CEP,CET,PE,D,CP,CR; input 3:0D; output TC; output 3:0Q; reg 3:0Q; wire CE;assign CE= CEP&CET;assign TC=CET&(Q=4b1111);always (posedge CP or negedge CR) if(CR)Q<=4b0000; else if(PE)Q<=D; else if(CE)Q<=Q; else Q<=Q+1b1;endmodule6.6.3module ripplecounter (Q0,Q1,Q2,Q3,CP,CR);output Q0,Q1,Q2,Q3;input CP,CR;D_FF FF0(Q0,Q0,CP,CR);D_FF FF1(Q1,Q1,Q0,CR);D_FF FF2(Q2,Q2,Q1,CR);D_FF FF3(Q3,Q3,Q2,CR);endmodulemodule D_FF(Q,D,CP,Rd); output Q; input D,CP,Rd; reg Q;always (negedge CP or negedge Rd) if(Rd)Q<=1b0;elseQ<=D;endmodule6.6.4module m10_counter(CE,CP,CR,Q); input CE,CP,CR;output 3:0Q;reg 3:0Q;always (posedge CP or negedge CR) if(CR)Q<=4b0000; else if(CE)begin if(Q>=4b1001) Q<=4b0000; else Q<=Q+1b1;endelse Q<=Q;endmodule6.6.5module Mealy_sequence_detector(A,CP,CR,Y); input A,CP,CR; output Y; reg Y; reg1:0current_state,next_state; parameter S0=2b00, S1=2b01, S2=2b11;always (negedge CP or negedgeCR)begin if(CR) current_state<=S0; else current_state<= next_state;endalways (current_state or A)begin case(current_state)S0:begin Y<=0; next_state<=(A=1)?S1:S0;endS1:begin Y<=0; next_state<=(A=1)?S2:S0;endS2:if(A=1) begin Y<=0;next_state<=S2;end else beginY<=1; next_state<=S0;enddefult:begin Y<=0; next_state<=S0;end endcaseendendmodule 6.6.6module Moore_mdl(Data,Q,CP,CR); input Data,CP,CR;output1:0 Q;reg1:0 state;parameter S0=2b00, S1=2b01, S2=2b10,S3=2b11;always (posedge CP or negedge CR)begin if(CR) state<=S0; elsecase(state) S0:if(Data)state<=S1; S1:if(Data)state<=S2;else state<=S3; S2:if(Data)state<=S3; S3:if(Data)state<=S0;endcaseendassign Q=state;endmodule 7.5.1module basketball24(TimerH,TimerL,Alarm,nRST,nPAUSE,CP); input nRST,nPAUSE,CP; wire nRST,nPAUSE,CP; output3:0 TimerH,TimerL;reg 3:0 TimerH,TimerL; output Alarm;assign Alarm=( TimerH,TimerL=8h00)&( nRST=1b1);always (posedge CP or negedge nRST or negedge nPAUSE) begin if(nRST) TimerH,TimerL<=8h24; else if (nPAUSE) TimerH,TimerL<= TimerH,TimerL; else if ( TimerH,TimerL=8h00) begin TimerH,TimerL<= TimerH,TimerL;end else if (TimerL=4h0) begin TimerH<= TimerH-1b1; TimerL<=4h9;end else begin TimerH<= TimerH; TimerL<= TimerL-1b1;endendendmodule 7.5.2module top_clock (Hour,Minute,Second,CP,nCR,EN,Adj_Min,Adj_Hour); input CP,nCR,EN,Adj_Min,Adj_Hour; output 7:0 Hour,Minute,Second;wire 7:0 Hour,Minute,Second;supplyl Vdd;wire MinL_EN,MinH_EN,Hour_EN;counter10 U1(Second3:0, nCR,EN,CP); counter6 U2(Second7:4, nCR,( Second3:0=4h9),CP); assign MinL_EN=Adj_Min?Vdd:(Second=8h59); assign MinH_EN=(Adj_Min&&(Minute3:0=4h9)| (Minute3:0=4h9)&&(Second=8h59);counter10 U3 (Minute3:0,nCR,MinL_EN,CP);counter6 U4 (Minute7:4,nCR,MinH_EN,CP);assign Hour_EN=Adj_Hour?Vdd:(Minute=8h59)&&(Second=8h59);counter24 U5 (Hour7:4,Hour3:0,nCR,Hour _EN,CP);endmodule module counter10 (Q, nCR,EN,CP); input CP, nCR,EN; output 3:0Q; reg 3:0Q;always (posedge CP or negedge nCR) begin if(nCR) Q<=4b0000; else if(EN) Q<=Q;else if(Q=4b1001) Q<=4b0000;else Q<=Q+1b1; endendmodule module counter6 (Q, nCR,EN,CP); input CP, nCR,EN; output 3:0Q; reg 3:0Q;always (posedge CP or negedge nCR) begin if(nCR) Q<=4b0000; else if(EN) Q<=Q;else if(Q=4b0101) Q<=4b0000;else Q<=Q+1b1; endendmodule module counter24 (CntH,CntL, nCR,EN,CP); input CP, nCR,EN; output 3:0 CntH,CntL; reg 3:0 CntH,CntL; reg CO;always (posedge CP or negedge nCR)begin if(nCR) CntH,CntL<=8h00;else if(EN) CntH,CntL<= CntH,CntL;else if(CntH>2)|(CntL>9)|( CntH=2)&&(CntL>=3) CntH,CntL<=8h00;else if(CntH=2)&&(CntL<3) begin CntH<= CntH;CntL<= CntL+1b1;endelse if(CntL=9) begin CntH<= CntH+1b1; CntL<=4b0000;endelse begin CntH<= CntH;CntL<= CntL+1b1;end endendmodule