基于VHDL的数字钟的设计.doc
顶层文件- Company: - Engineer: - - Create Date: 09:40:47 01/14/2014 - Design Name: - Module Name: digital_clock - Behavioral - Project Name: - Target Devices: - Tool versions: - Description: - Dependencies: - Revision: - Revision 0.01 - File Created- Additional Comments: -library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;ENTITY digital_clock IS PORT(setup : IN STD_LOGIC;-预置脉冲手动set : IN STD_LOGIC;-upd0选择工作模式clk : IN STD_LOGIC;-输入1Khz脉冲 需要经过1000分频 产生1hz脉冲tn : IN STD_LOGIC;-相当于题目要求中的up 为高时 预置+1 为低时-1en : IN STD_LOGIC;-使能H_Year : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);H_Year1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);M_Mon : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);M_Mon1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);S_Day : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);S_Day1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END digital_clock;ARCHITECTURE bdf_type OF digital_clock IS COMPONENT daymony1PORT(clk0 : IN STD_LOGIC; en : IN STD_LOGIC; lock : IN STD_LOGIC_VECTOR(2 DOWNTO 0); da0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); da1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); mo0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); mo1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); ya0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); ya1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COMPONENT;COMPONENT fenpinPORT(upd0 : IN STD_LOGIC;-外接顶层set clk : IN STD_LOGIC;-外接顶层f10 f_clk : OUT STD_LOGIC;-分频输出为1hz lock : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)-计数set脉冲 000-111循环产生工作模式);END COMPONENT;COMPONENT s_m_hourPORT(clk0 : IN STD_LOGIC; en : IN STD_LOGIC; lock : IN STD_LOGIC_VECTOR(2 DOWNTO 0); co : OUT STD_LOGIC; h0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); h1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COMPONENT;COMPONENT yuzhisPORT(clk1 : IN STD_LOGIC; tn : IN STD_LOGIC; en : IN STD_LOGIC; lock : IN STD_LOGIC_VECTOR(2 DOWNTO 0); da0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); da1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); mo0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); mo1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); ya0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); ya1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COMPONENT;COMPONENT s_m_yuz1PORT(clk1 : IN STD_LOGIC; tn : IN STD_LOGIC; en : IN STD_LOGIC; lock : IN STD_LOGIC_VECTOR(2 DOWNTO 0); h0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); h1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COMPONENT;COMPONENT xuanze1 port( en : in std_logic; lock : in std_logic_vector(2 downto 0); -工作模式选择 a0 : in std_logic_vector(3 downto 0); a1 : in std_logic_vector(3 downto 0);-s b0 : in std_logic_vector(3 downto 0); b1 : in std_logic_vector(3 downto 0);-mc0 : in std_logic_vector(3 downto 0); c1 : in std_logic_vector(3 downto 0);-h d0 : in std_logic_vector(3 downto 0); d1 : in std_logic_vector(3 downto 0);-se0 : in std_logic_vector(3 downto 0); e1 : in std_logic_vector(3 downto 0);-m f0 : in std_logic_vector(3 downto 0); f1 : in std_logic_vector(3 downto 0);-h s0,s1 : out std_logic_vector(3 downto 0); m0,m1 : out std_logic_vector(3 downto 0); h0,h1 : out std_logic_vector(3 downto 0) );END COMPONENT;COMPONENT xuanze2 port( en : in std_logic; lock : in std_logic_vector(2 downto 0); -工作模式选择 a0 : in std_logic_vector(3 downto 0); a1 : in std_logic_vector(3 downto 0);-日 b0 : in std_logic_vector(3 downto 0); b1 : in std_logic_vector(3 downto 0);-月c0 : in std_logic_vector(3 downto 0); c1 : in std_logic_vector(3 downto 0);-年 d0 : in std_logic_vector(3 downto 0); d1 : in std_logic_vector(3 downto 0);-日e0 : in std_logic_vector(3 downto 0); e1 : in std_logic_vector(3 downto 0);-月 f0 : in std_logic_vector(3 downto 0); f1 : in std_logic_vector(3 downto 0);-年 da0,da1 : out std_logic_vector(3 downto 0); mo0,mo1 : out std_logic_vector(3 downto 0); ya0,ya1 : out std_logic_vector(3 downto 0) );END COMPONENT;COMPONENT time_showPORT( en : IN STD_LOGIC; lock : IN STD_LOGIC_VECTOR(2 DOWNTO 0);-显示切换义马管具体显示就不写了只解决显示切换模块 S_s0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_s1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_m0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_m1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_h0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_h1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_da0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_da1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_mo0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_mo1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_ya0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_ya1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); aH_Year : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);aH_Year1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);aM_Mon : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);aM_Mon1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);aS_Day : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);aS_Day1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COMPONENT;SIGNALSYNTHESIZED_WIRE_8 : STD_LOGIC;-连接工作时钟SIGNALSYNTHESIZED_WIRE_1 : STD_LOGIC;-连接时分秒的进位输出SIGNALSYNTHESIZED_WIRE_9 : STD_LOGIC_VECTOR(2 DOWNTO 0);-连接lockSIGNAL s0a0: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL s1a1: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m0b0: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m1b1: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL h0c0: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL h1c1: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL s0d0: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL s1d1: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m0e0: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m1e1: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL h0f0: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL h1f1: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL da0a0: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL da1a1: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL mo0b0: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL mo1b1: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL ya0c0: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL ya1c1: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL da0d0: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL da1d1: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL mo0e0: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL mo1e1: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL ya0f0: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL ya1f1: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m1: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m2: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m3: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m4: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m5: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m6: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m7: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m8: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m9: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m10: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m11: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL m12: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN u1 : daymony1PORT MAP(clk0 => SYNTHESIZED_WIRE_8, en => SYNTHESIZED_WIRE_1, lock => SYNTHESIZED_WIRE_9, da0 => da0a0, da1 => da1a1, mo0 => mo0b0, mo1 => mo1b1, ya0 => ya0c0, ya1 => ya1c1);-u2 : fenpinPORT MAP(upd0 =>set, clk => clk, f_clk=> SYNTHESIZED_WIRE_8, lock => SYNTHESIZED_WIRE_9);-u3 : s_m_hourPORT MAP(clk0 => SYNTHESIZED_WIRE_8, en => en, lock => SYNTHESIZED_WIRE_9, co => SYNTHESIZED_WIRE_1, h0 => h0c0, h1 => h1c1, m0 => m0b0, m1 => m1b1, s0 => s0a0, s1 => s1a1);u4: yuzhisPORT MAP(clk1 => setup, tn => tn, en => en, lock => SYNTHESIZED_WIRE_9, da0 => da0d0, da1 => da1d1, mo0 => mo0e0, mo1 => mo1e1, ya0 => ya0f0, ya1 => ya1f1);u5 : s_m_yuz1PORT MAP( clk1 => setup, tn => tn, en => en, lock => SYNTHESIZED_WIRE_9, h0 => h0f0, h1 => h1f1, m0 => m0e0, m1 => m1e1, s0 => s0d0, s1 => s1d1);u6 : xuanze1PORT MAP ( en => en, lock => SYNTHESIZED_WIRE_9, a0 => s0a0, a1 => s1a1, b0 => m0b0, b1 => m1b1,c0 => h0c0, c1 => h1c1, d0 => s0d0, d1 => s1d1,e0 => m0e0, e1 => m1e1, f0 => h0f0, f1 => h1f1, s0 => m1,s1 => m2, m0 => m3,m1 => m4, h0 => m5,h1 => m6 );u7 : xuanze2PORT MAP ( en => en, lock => SYNTHESIZED_WIRE_9,-没完成 a0 => da0a0, a1 => da1a1, b0 => mo0b0, b1 => mo1b1,c0 => ya0c0, c1 => ya1c1, d0 => da0d0, d1 => da1d1,e0 => mo0e0, e1 => mo1e1, f0 => ya0f0, f1 => ya1f1, da0 => m7, da1 => m8, mo0 => m9, mo1 => m10, ya0 => m11, ya1 => m12 );u8 : time_showPORT MAP ( en => en, lock => SYNTHESIZED_WIRE_9,-显示切换义马管具体显示就不写了只解决显示切换模块 S_s0 => m1, S_s1 => m2, S_m0 =>m3, S_m1 => m4, S_h0 => m5, S_h1 => m6, S_da0 => m7, S_da1 => m8, S_mo0 => m9, S_mo1 => m10, S_ya0 => m11, S_ya1 => m12,aH_Year => H_Year , aH_Year1 => H_Year1,aM_Mon => M_Mon,aM_Mon1 => M_Mon1,aS_Day => S_Day,aS_Day1 => S_Day1 );END bdf_type;daymony1年月日library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;entity daymony1 is port( clk0 : in std_logic; da0,da1 : out std_logic_vector(3 downto 0); mo0,mo1 : out std_logic_vector(3 downto 0); ya0,ya1 : out std_logic_vector(3 downto 0); en : in std_logic;-en接上一个模块小时的进位 lock : in std_logic_vector(2 downto 0) ); end daymony1;architecture Behavioral of daymony1 is signal dat0 : std_logic_vector(3 downto 0):="0110"signal dat1 : std_logic_vector(3 downto 0):="0001"signal mon0 : std_logic_vector(3 downto 0):="0001"signal mon1 : std_logic_vector(3 downto 0):="0000"signal yea0 : std_logic_vector(3 downto 0):="0100"signal yea1 : std_logic_vector(3 downto 0):="0001"signal day_out,month_out:std_logic;-程序内部天和月的进位，也可放于前面设为bufferbeginda0<=dat0;da1<=dat1;mo0<=mon0;mo1<=mon1;ya0<=yea0;ya1<=yea1;-年月日赋初值P1:process (clk0,en,lock)-天的输出，分大月和小月，以及二月beginif en='1'then -时分秒模块有进位使能年月日 if lock="001"then if clk0'event AND clk0='1'then if (mon0="0001"and mon1="0000")or(mon0="0011"and mon1="0000") or(mon0="0101"and mon1="0000")or(mon0="0111"and mon1="0000") or(mon0="1000"and mon1="0000")or(mon0="0000"and mon1="0001") or(mon0="0010"and mon1="0001")then -1 3 5 7 8 10 12月为31天 if dat0="0001" and dat1="0011"then dat0<="0001"dat1<="0000"day_out<='1' elsif dat0="1001"then dat0<="0000"dat1<=dat1+1;day_out<='0' else dat0<=dat0+'1'dat1<=dat1;day_out<='0' end if; elsif(mon0="0100"and mon1="0000")or(mon0="0110"and mon1="0000") or(mon0="1001"and mon1="0000")or(mon0="0001"and mon1="0001")then -4 6 9 11月份30天 if dat0="0000" and dat1="0011"then dat0<="0001"dat1<="0000"day_out<='1' elsif dat0="1001"then dat0<="0000"dat1<=dat1+1;day_out<='0' else dat0<=dat0+'1'dat1<=dat1;day_out<='0' end if; Else -对闰年的判断2月29数码管只显示年后两位 前两位默认为20 故只要后两位能被4整除即使闰年 if(yea1="0000"OR yea1="0010"OR yea1="0100"OR yea1="0110" OR yea1="01000")AND(yea0="0000" OR yea0="0100"OR yea0="01000")OR (yea1="0001" OR yea1="0011" OR yea1="0101"OR yea1="0111" OR yea1="1001")AND(yea0="0010"OR yea0="0110") THEN if dat0="1001" and dat1="0010"then dat0<="0001"dat1<="0000"day_out<='1' elsif dat0="1001"then dat0<="0000"dat1<=dat1+'1'day_out<='0' else dat0<=dat0+'1'dat1<=dat1;day_out<='0' end if; else-不是闰年，二月份28天 if dat0="1000" and dat1="0010"then dat0<="0001"dat1<="0000"day_out<='1' elsif dat0="1001"then dat0<="0000"dat1<=dat1+'1'day_out<='0' else dat0<=dat0+'1'dat1<=dat1;day_out<='0' end if; end if;-判断闰年的语句 end if;-判断月份的语句 end if;-对应clk0 end if;-对应lock end if;-对应使能end process P1;P2:process (day_out,lock)-对月的输出begin if lock="001"then if day_out'event AND day_out='1'then -天数产生进位使月份加一 if mon0="0010" and mon1="0001"then mon0<="0001"mon1<="0000"month_out<='1'-到十二月份后重新回到一月份产生月进位给年 elsif mon0="1001"then
