verilog秒表代码.doc

module stopwatch(clk,out,reset,cin,ocom,count);output3:0 ocom;output7:0 out;output count;input cin,clk,reset;reg 7:0 out_ms,out_s;reg7:0 out_min;reg7:0 out;reg3:0 ocom;reg3:0 in_out;reg clk_m,clk_n,clk_p;reg1:0 select;reg count;integer count_clk,count_cp,count_tp;always (posedge clk)if (count_cp = 50000) /50MHZ做50000次分频，取反后得到2ms的时间begin count_cp = 0;clk_n = clk_n;end else count_cp = count_cp + 1;always (posedge clk)if (count_clk = 25000000) /50MHZ做25000000次分频，取反后得到1s的时间begin count_clk = 0;clk_m = clk_m;end else count_clk = count_clk + 1;always (posedge clk)if (count_tp = 250000) /50MHZ做250000次分频，取反后得到0.01s的时间begin count_tp = 0;clk_p = clk_p;end else count_tp = count_tp + 1;always (posedge clk_n) /2ms的数码管的扫描select=select + 1;always (select) /数码管的扫描begincase(select)2'b00 : begin ocom3:0=4'b1110;in_out = out_s3:0; end2'b01 : begin ocom3:0=4'b1101;in_out = out_s7:4; end2'b10 : begin ocom3:0=4'b1011;in_out = out_ms3:0; end2'b11 : begin ocom3:0=4'b0111;in_out = out_ms7:4; endendcaseendalways (posedge clk_p)beginif(!reset) /若reset为低电平，四位数码管清零beginout_ms <= 0;out_s <=0;endelse if(cin) /秒表计数 beginif(out_s3:0=9)beginout_s3:0 <= 0;if(out_s7:4=9)beginout_s7:4<=0; if(out_ms3:0=9)beginout_ms3:0 <= 0;if(out_ms7:4=5)out_ms7:4 <= 0;elseout_ms7:4 <= out_ms7:4+1; endelseout_ms3:0 <= out_ms3:0+1;endelseout_s7:4=out_s7:4+1; end elseout_s3:0=out_s3:0+1;endendalways (in_out) begincase(in_out) /数码管的绑定4'b0000 : out7:0=8'b1001_0000;4'b0001 : out7:0=8'b1001_1111;4'b0010 : out7:0=8'b0101_1000;4'b0011 : out7:0=8'b0001_1001;4'b0100 : out7:0=8'b0001_0111;4'b0101 : out7:0=8'b0011_0001;4'b0110 : out7:0=8'b0011_0000;4'b0111 : out7:0=8'b1001_1101;4'b1000 : out7:0=8'b0001_0000;4'b1001 : out7:0=8'b0001_0001;default : out7:0=8'bx;endcaseendendmodule