885191354基于CPLD的十字路口交通灯设计程序.doc
基于CPLD的十字路口交通灯设计说明：横向红灯纵向绿灯30秒；横向红灯纵向黄灯5秒；横向黄灯纵向红灯5秒；横向绿灯纵向红灯50秒（假设横向的车流量大，所以通行时间长）；横向黄灯纵向红灯5秒；横向红灯纵向黄灯5秒。（循环上述步骤）。 RTL视图：（四个模块一目了然） 芯片：alter公司的MAX II 系列EPM240T100C5Verilog代码：（由于特权同学的键盘前两天被折腾了，有部分字母按键失灵，所以写程序的时候是软硬键盘一起使，郁闷的直接连注释都省了。） （顶层模块）module traffic(clk,rst,row,light_v,led,ledseg); input clk;input rst;output3:0 row;/ NWSEoutput2:0 light_v;/red,yellow,greenoutput5:0 led;output7:0 ledseg;wire2:0 light0_reg,light1_reg;wire second;wire clk_50k;wire6:0 count;clk1000divclk1000div(.clk(clk),.rst(rst),.clk_50k(clk_50k);clkdivclkdiv(.clk(clk),.rst(rst),.second(second);lightlight(.rst(rst),.second(second),.light0_reg(light0_reg),.light1_reg(light1_reg),.count(count);light_dislight_dis(.clk(clk_50k),.rst(rst),.count(count),.light0_reg(light0_reg),.light1_reg(light1_reg),.row(row),.light_v(light_v),.led(led),.ledseg(ledseg); endmodule (该模块是1000分频产生50KHz信号，主要用于液晶或者交通灯的动态显示定时)module clk1000div(clk,rst,clk_50k); input clk;input rst;output clk_50k; reg9:0 div;reg clk_50k;always (posedge clk) beginif(!rst) begindiv <= 0;clk_50k <= 0;endelse beginif(div=999) beginclk_50k <= clk_50k;div <= 0; endelse begin div <= div+1; endendend endmodule (1Hz分频模块，用于交通灯的定时)module clkdiv(clk,rst,second); input clk;input rst;output second;reg27:0 num;reg second;always (posedge clk) beginif(!rst) beginnum <= 0;second <= 0;endelse beginnum <= num+28'd1;if(num=28'h2faf080) beginsecond <= second;num <= 0;endendend endmodule （该模块主要用于计算倒计时数值和交通灯的排选）module light(rst,second,light0_reg,light1_reg,count); input rst;input second;output2:0 light0_reg,light1_reg;output6:0 count;reg6:0 count;reg6:0 state;reg2:0 light0_reg,light1_reg;always (posedge second) beginif(!rst) beginstate <= 0;endelse beginif(state = 7'd99) beginstate <= 0;endelse beginstate <= state+1; endendendalways (state) beginif(state<30) begincount <= 29-state;light0_reg <= 3'b001;light1_reg <= 3'b100;endif(state>29 && state<35) begincount <= 34-state;light0_reg <= 3'b010;light1_reg <= 3'b100;endif(state>34 && state<40) begincount <= 39-state;light0_reg <= 3'b100;light1_reg <= 3'b010;endif(state>39 && state<90) begincount <= 89-state;light0_reg <= 3'b100;light1_reg <= 3'b001;endif(state>89 && state<95) begin count <= 94-state;light0_reg <= 3'b100;light1_reg <= 3'b010;endif(state>94 && state<100) begin count <= 99-state;light0_reg <= 3'b010;light1_reg <= 3'b100;endend endmodule （该模块进行数码管倒计时显示和交通灯显示控制）module light_dis(clk,rst,count,light0_reg,light1_reg,row,light_v,led,ledseg); input clk;input rst;input6:0 count;input2:0 light0_reg,light1_reg;output5:0 led;output7:0 ledseg;output3:0 row;/ NWSEoutput2:0 light_v;/ red,yellow,greenreg3:0 row;/ NWSEreg2:0 light_v;/ red,yellow,greenreg state;reg5:0 led;reg7:0 ledseg;reg7:0 ledreg1:0;reg7:0 led_shu9:0;always (posedge clk) beginif(!rst) beginstate <= 0;led_shu0 <= 8'h3f;led_shu1 <= 8'h06;led_shu2 <= 8'h5b;led_shu3 <= 8'h4f;led_shu4 <= 8'h66;led_shu5 <= 8'h6d;led_shu6 <= 8'h7d;led_shu7 <= 8'h07;led_shu8 <= 8'h7f;led_shu9 <= 8'h6f;endelse beginstate <= state+1;if(count<10) beginledreg0 <= led_shucount; ledreg1 <= led_shu0;endelse if(count<20) beginledreg0 <= led_shucount-10; ledreg1 <= led_shu1;endelse if(count<30) beginledreg0 <= led_shucount-20; ledreg1 <= led_shu2;endelse if(count<40) beginledreg0 <= led_shucount-30; ledreg1 <= led_shu3;endelse beginledreg0 <= led_shucount-40; ledreg1 <= led_shu4;endendendalways (state) begincase (state)0: beginrow <= 4'b0101;light_v <= light0_reg;led <= 6'b111110;ledseg <= ledreg1;end1: beginrow <= 4'b1010;light_v <= light1_reg;led <= 6'b111101;ledseg <= ledreg0;enddefault: ;endcaseend endmodule
