EDA课程设计数字钟 .doc
EDA 期 末 设 计设计名称： 数 字 钟 学 院：物理与电子工程学院 年 级：2008 级 7 班 姓 名：* 学 号：2008070709 2010 年 5 月 25 日一 实验目的练习综合设计能力，设计一个含有时、分、秒的时钟，并且可以设置、清除、12/24小时工作模式的切换、仿电台整点报时。二 实验内容基本要求（1） 具有“秒”、“分”、“时”计时功能（2） 能进行24/12小时制计时模式切换拓展要求（1） 具有校时设置和清除功能，能够对“分”和“时”进行调整（2） 具有整点报时功能三 实验原理第一个模块为计时、校时、响铃模块，第二个为12与24进制相互转换。四 本实验介绍（各按钮所对应实验箱按钮键引脚图）（1） 功能：a具有“秒”、“分”、“时”计时功能b能进行24/12小时制计时模式切换, 具有校时设置和清除功能，能够对“分”和“时”进行调整c.在59分56秒、57秒、58秒、59秒报时（2）按钮功能：CLK:计数1HZ脉冲，CLK1024和CLK512报时脉冲； EN=0为校时模式，en=1为计数模式； swich=1则12进制到24进制,swich=0则24到12进制； 第三和第八数码管为标志：A:上午标志d:下午标志 ， E：24进制计数模式标志SHI,FEN:对时、分的校正；都按FEN下时，对分低位校正，按下SHI对时校正，按SHI和FEN下分，对高位分校正（均自动校正）。（2） 系统对应按钮：键1：计数/校时模式控制；键2：分低位校时；键3：复位； 键4：时位校时；键5：进制转换五 实验结果视屏：学习实验视频 - 专辑 - 优酷视频六 设计程序：(1)-*计数/校时/响铃*LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SHIFENMIAO ISPORT(CLK,RST, CLK0,CLK1,EN,SHI1,FEN1 : IN STD_LOGIC;CQ: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);- 计数输出SIGN:OUT STD_LOGIC;DXWSIGN:OUT STD_LOGIC );END ENTITY SHIFENMIAO;ARCHITECTURE BHAVE1 OF SHIFENMIAO ISSIGNAL X : STD_LOGIC; SIGNAL AB : STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL CQI : STD_LOGIC_VECTOR(31 DOWNTO 0);BEGINAB<=SHI1&FEN1;Q1:PROCESS (CLK,RST, EN)VARIABLE SXSIGN:STD_LOGIC;BEGINIF RST = '1' THENCQI <= (OTHERS => '0');SXSIGN:='0'- 计数器清零复位ELSEIF CLK'EVENT AND CLK = '1' THEN- 上升沿判断IF EN = '1' THENIF CQI(3 DOWNTO 0) < "1001" THEN- 比较低4位CQI <= CQI + 16#1#;- 计数加1ELSIF CQI(7 DOWNTO 4) < "0101" THEN- 比较高4位CQI <= CQI + 16#10#;CQI(3 DOWNTO 0) <="0000" - 低4位清零-MIAO计时ELSIF CQI(15 DOWNTO 12) < "1001" THENCQI <= CQI + 16#1000#;CQI(7 DOWNTO 4) <= "0000"CQI(3 DOWNTO 0) <="0000"ELSIF CQI(19 DOWNTO 16) < "0101" THENCQI <= CQI + 16#10000#;CQI(15 DOWNTO 12) <= "0000"CQI(7 DOWNTO 4) <= "0000"CQI(3 DOWNTO 0) <="0000"-FEN计时ELSIF CQI(27 DOWNTO 24) < 9 THENCQI <= CQI + 16#1000000#;CQI(19 DOWNTO 16) <= "0000"CQI(15 DOWNTO 12) <= "0000"CQI(7 DOWNTO 4) <= "0000"CQI(3 DOWNTO 0) <="0000"ELSIF CQI(31 DOWNTO 28)<1 THENCQI <= CQI+16#10000000#;CQI(27 DOWNTO 24)<="0000"CQI(19 DOWNTO 16) <= "0000"CQI(15 DOWNTO 12) <= "0000"CQI(7 DOWNTO 4) <= "0000"CQI(3 DOWNTO 0) <="0000"-SHI计时END IF;-*校时*ELSE CASE AB ISWHEN"01"=>IF CQI(15 DOWNTO 12) <"1001" THEN CQI(15 DOWNTO 12) <= CQI(15 DOWNTO 12)+1;ELSE CQI(15 DOWNTO 12) <="0000" END IF;WHEN"10"=>IF CQI(27 DOWNTO 24) <"1001" THEN CQI(27 DOWNTO 24) <= CQI(27 DOWNTO 24)+1;ELSE CQI(31 DOWNTO 28) <="0001"CQI(27 DOWNTO 24) <="0000"END IF;WHEN"11"=>IF CQI(19 DOWNTO 16)<"0101" THEN CQI(19 DOWNTO 16)<=CQI(19 DOWNTO 16)+"0001"ELSE CQI(19 DOWNTO 16)<="0000" END IF;WHEN OTHERS =>NULL;END CASE;END IF;END IF;END IF;IF CQI(31 DOWNTO 28)="0001"AND CQI(27 DOWNTO 24)="0010" THEN-清零CQI(19 DOWNTO 16) <= "0000"CQI(31 DOWNTO 24)<="00000000"CQI(15 DOWNTO 12) <= "0000"SXSIGN:= NOT SXSIGN; -上下午标志CQI(7 DOWNTO 4) <= "0000"CQI(3 DOWNTO 0) <="0000"END IF;IF SXSIGN='0' THEN CQI(11 DOWNTO 8)<="1010" CQI(23 DOWNTO 20)<="1010"ELSE CQI(11 DOWNTO 8)<="1101" CQI(23 DOWNTO 20)<="1101"END IF;CQ<=CQI;DXWSIGN<=SXSIGN;END PROCESS Q1; -*响铃*Q2:PROCESS(CQI)BEGINIF CQI(19 DOWNTO 16) = "0101"AND CQI(15 DOWNTO 12) = "1001"AND CQI(7 DOWNTO 4) ="0101" THENIF CQI(3 DOWNTO 0) = "0110" THENX<=CLK0;ELSIF CQI(3 DOWNTO 0) = "0111" THENX<=CLK0;ELSIF CQI(3 DOWNTO 0) = "1000" THENX<=CLK0;ELSIF CQI(3 DOWNTO 0) = "1001" THENX<=CLK1;END IF;END IF;END PROCESS Q2; SIGN<=X; END ARCHITECTURE BHAVE1;(2)-*12进制与24进制的相互转换*LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY EH12SWICH24 ISPORT(CQI24:OUT STD_LOGIC_VECTOR(31 DOWNTO 0);SIGN12:IN STD_LOGIC; SWSIGN12:IN STD_LOGIC; CQI12:IN STD_LOGIC_VECTOR(31 DOWNTO 0);END ENTITY;ARCHITECTURE BHAVE10 OF EH12SWICH24 IS SIGNAL CQI12TO24: STD_LOGIC_VECTOR(31 DOWNTO 0);BEGINSW1:PROCESS(SIGN12,SWSIGN12)BEGINIF SWSIGN12='1' THENIF SIGN12='0' THEN -上午不变CQI12TO24<=CQI12; -12到24进制ELSE CQI12TO24(31 DOWNTO 24)<=CQI12(31 DOWNTO 24)+"00010010"-下午加12CQI12TO24(11 DOWNTO 8 )<="1110"CQI12TO24(23 DOWNTO 20 )<="1110" -24进制标志CQI12TO24(19 DOWNTO 12)<=CQI12(19 DOWNTO 12);CQI12TO24(7 DOWNTO 0)<=CQI12(7 DOWNTO 0);END IF;ELSE-*24到12进制CQI12TO24<=CQI12;END IF;CQI24<=CQI12TO24;END PROCESS SW1;END BHAVE10;(3)-*顶层文件设计*LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SHUZHIZHONG ISPORT(CLK,RST,CLK1024,CLK512, EN,SWICH,SHI,FEN: IN STD_LOGIC;COUT: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);SIGN:OUT STD_LOGIC );END ENTITY SHUZHIZHONG;ARCHITECTURE STRUC OF SHUZHIZHONG IS COMPONENT SHIFENMIAO PORT(CLK,RST,CLK0,CLK1, EN,SHI1,FEN1 : IN STD_LOGIC;CQ: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);SIGN:OUT STD_LOGIC;DXWSIGN:OUT STD_LOGIC ); END COMPONENT SHIFENMIAO; COMPONENT EH12SWICH24 PORT(CQI24:OUT STD_LOGIC_VECTOR(31 DOWNTO 0);SIGN12:IN STD_LOGIC; SWSIGN12:IN STD_LOGIC; CQI12:IN STD_LOGIC_VECTOR(31 DOWNTO 0);END COMPONENT;SIGNAL D1:STD_LOGIC;SIGNAL D2:STD_LOGIC_VECTOR(31 DOWNTO 0);BEGINU1: SHIFENMIAO PORT MAP(CLK=>CLK,EN=>EN,RST=>RST,SIGN=>SIGN,CLK0=>CLK512,CLK1=>CLK1048, CQ=>D2,DXWSIGN=>D1,SHI1=>SHI,FEN1=>FEN);U2: EH12SWICH24 PORT MAP(CQI24=>COUT,CQI12=>D2,SIGN12=>D1,SWSIGN12=>SWICH);END STRUC;七 程序编译、仿真（1） 编译结果（2）仿真波形八 引脚配置九实验总结1. 实验中遇到许多难题，比如信号不能多次赋值（解决：做多个元件），分频比较难实现（解决：外部输入脉冲，替代分频脉冲功能）2. 学习心得：做实验室要仔细写程序，特别是不要换小错误比如：前后结构体名不一致，少写“；”子类的小错误。
