EDA技术与实践综合设计报告.doc

北 华 航 天 工 业 学 院综合实践总结报告 综合实践名称： EDA技术与实践 年历日历设计 综合实践地点、时间 教十EDA实验室 2014-2015-2学期第1317周 专业班级： 13251 姓 名： 李露 陈泽东 李泽宙 学号： 201310194 201310167 201310193 指导教师姓名： 薛 瑞 完 成 时 间： 2015 年 6 月 20 日一、综合实践目的1.通过编写VHDL程序，结合硬件电路设计，实现年·月·日的计时 功能。同时将计时结果通过8个七段数码管显示，并可通过两个按键，对计数时钟的有关参数进行调整。2.学会使用QUARTUS软件下载调试程序，用调试程序将学习板调试成功。锻炼学生的动手能力以及提高学生的综合专业素质。 二、综合实践理论基础和核心内容根据系统的设计要求，计时电路可分为计日电路，计月电路，计年电路等三个子模块，这三个子模块必须都具有预置，计数和进位功能，设计思想如下：（1) 计日电路：将计时电路产生的进位脉冲信号作为计日电路的计数时钟信号，通过系统辨认，确定本月总天数X（包括28，29，30，31四种情况），待计数至X+1瞬间，进位，计月电路加1，而计日电路返回1重新开始计数。（2) 计月电路：将计日电路产生的进位脉冲信号作为计月电路的计时时钟信号，待计时至12瞬间，进位，计年电路加1，而计月电路返回1重新开始计数。（3) 计年电路：将计月电路产生的进位脉冲信号作为时钟计年电路的计数时钟信号，待计数至100瞬间，计年电路返回0重新开始计数。（4) 对于系统中的时间调整电路，拟通过模式和调整两个外部按件完成。模式键负责切换正常时间计数模式和时间调整模式，调整键负责在时间调整模式之下，对当前模式的计数结果进行调整。三、综合实践具体内容和记录（图、表或程序等）1·Tian程序（李露）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity tian isport(clk,a,b:in std_logic; t1:out std_logic_vector(3 downto 0); t2:out std_logic_vector(7 downto 4); cout:out std_logic); end tian;architecture one of tian issignal q1:std_logic_vector(3 downto 0);signal q2:std_logic_vector(7 downto 4);signal ab :std_logic_vector(1 downto 0);beginprocess(clk,a,b)beginif clk'event and clk='1' thenq1 <= q1+1;if q1 =9 then q1 <="0000"q2 <= q2+1;end if;ab <= a&b;case ab iswhen "00"=> -当ab=00时，yue输出31天if q2=3 and q1=1 then q2<="0000"q1<="0001"cout<='1'else cout <= '0'end if;when "01"=> -当ab=01时，yue输出30天if q2=3 and q1=0 then q2<="0000"q1<="0001"cout<='1'else cout <= '0'end if;when "10"=> -当ab=10时，yue输出28天if q2=2 and q1=8 then q2<="0000"q1<="0001"cout<='1'else cout <= '0'end if;when "11"=> -当ab=11时，yue输出29天if q2=2 and q1=9 then q2<="0000"q1<="0001"cout<='1'else cout <= '0'end if;when others=>null;end case;end if;end process;t1<=q1;t2<=q2;end one;仿真 31天 30天28天29天2·Yue程序（陈泽东）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yue isport(clk,run:in std_logic;y1:out std_logic_vector(3 downto 0);y2:out std_logic_vector(7 downto 4);a,b,cout:out std_logic);end yue;architecture one of yue issignal q1,q2:std_logic_vector(3 downto 0);signal q2q1:std_logic_vector(7 downto 0);beginprocess(clk,run)beginif clk'event and clk='1' then q1<=q1+1;if q1=9 then q1<=(others=>'0');q2<=q2+1;end if;if q2=1 and q1=2 thenq2<="0000"q1<="0001"cout<='1'else cout<='0'end if;end if;q2q1<=q2&q1;case q2q1 iswhen"00000001"=>a<='0'b<='0' -当为1月时，a=0 b=0 为31天when"00000010"=> if run='1' then a<='1'b<='1'else a<='1'b<='0' end if; -当为2月时，如果是闰年a=1 b=1 为29天，否则a=1 b=0 为28天when"00000011"=>a<='0'b<='0' -当为3月时，a=0 b=0 为31天when"00000100"=>a<='0'b<='1' -当为4月时，a=0 b=1 为30天when"00000101"=>a<='0'b<='0' -当为5月时，a=0 b=0 为31天when"00000110"=>a<='0'b<='1' -当为6月时，a=0 b=1 为30天when"00000111"=>a<='0'b<='0' -当为7月时，a=0 b=0 为31天when"00001000"=>a<='0'b<='0' -当为8月时，a=0 b=0 为31天when"00001001"=>a<='0'b<='1' -当为9月时，a=0 b=1 为30天when"00010000"=>a<='0'b<='0' -当为10月时，a=0 b=0 为31天when"00010001"=>a<='0'b<='1' -当为11月时，a=0 b=1 为30天when"00010010"=>a<='0'b<='0' -当为12月时，a=0 b=0 为31天when others=>null;end case;y1<=q1;y2<=q2;end process;end one;仿真3·Nian程序（李泽宙）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity nian isport (clk:in std_logic; n1,n2:out std_logic_vector(3 downto 0); run,cout:out std_logic); end nian;architecture one of nian issignal q1,q2,q3:std_logic_vector(3 downto 0);beginprocess(clk)beginif clk'event and clk='1'then -如果clk=1时，q1加1q1<=q1+1;if q1=9 then q1<=(others=>'0'); -如果q1=9,q1清零，q2加1q2<=q2+1;end if;if q2=9 and q1=9 then q1<="0000" -如果q1=9,q2=9,q1、q2清零，进位。否则不进位q2<="0000"cout<='1'else cout<='0'end if;end if;end process;process(clk)beginif clk'event and clk='1'then -如果clk=1,q3加1q3<=q3+1;if q3=3 then q3<=(others=>'0'); -如果q3=3则q3清零 run=1否则run=0run<='1'else run<='0'end if;end if;n1 <= q1;n2 <= q2;end process;end one;仿真4·Nian2程序（李泽宙）LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY nian2 IS PORT(clk:IN STD_LOGIC; n3,n4:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END ENTITY nian2; ARCHITECTURE one OF nian2 IS SIGNAL q1:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000" SIGNAL q2:STD_LOGIC_VECTOR(3 DOWNTO 0):="0010" SIGNAL q3:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(clk) BEGIN IF clk'EVENT AND clk='1' THEN -如果clk=1时，q1加1 q1<=q1+'1' IF q1=9 THEN -如果q1=9,q1q2加1 q1<="0000" q2<=q2+'1' END IF; IF q2=9 AND q1=9 THEN -如果q1=9,q2=9,q1、q2清零 q2<="0000" q1<="0000" END IF; END IF; n3<=q1;n4<=q2; END PROCESS; END one;仿真5·Seltime程序扫描（李露）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity seltime isport(clk1:in std_logic;t1,t2,y1,y2,n1,n2,n3,n4:in std_logic_vector(3 downto 0);daout :out std_logic_vector(3 downto 0);dp: out std_logic;s:out std_logic_vector(3 downto 0);sel :out std_logic_vector(3 downto 0);end seltime;architecture fun of seltime issignal count :std_logic_vector(3 downto 0);begins<="1011"sel<=count;process(clk1)beginif(clk1'event and clk1='1')thenif(count>="0111")thencount<="0000"elsecount<=count+1;end if;end if;case count isWHEN "0000" => DAOUT <=t1; DP<='0'-sel为“0000”时，扫描天个位，DP点不亮WHEN "0001" => DAOUT <= t2;DP<='0'-sel为“0001”时，扫描天十位，DP点不亮WHEN "0010"=> DAOUT <= y1;DP<='1'-sel为“0010”时，扫描月个位，DP点亮WHEN "0011"=> DAOUT <=y2;DP<='0'-sel为“0011”时，扫描月十位，DP点不亮WHEN "0100"=> DAOUT <= n1;DP<='1'-sel为“0100”时，扫描年个位，DP点亮WHEN "0101"=> DAOUT <= n2;DP<='0'-sel为“0101”时，扫描年十位，DP点不亮WHEN "0110"=> DAOUT <= n3;DP<='0'-sel为“0110”时，扫描年百位，DP点不亮WHEN OTHERS=> DAOUT <=n4;DP<='0'-sel为“0111”时，扫描年千位，DP点不亮end case;end process;end fun;仿真6·Tiao程序校对（陈泽东）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY tiao ISPORT( K1,K2 :IN STD_LOGIC; CLK,TI,YI,NI:IN STD_LOGIC; TL,YO,NO,NO1 :OUT STD_LOGIC; L1,L2,L3,L4:OUT STD_LOGIC);END tiao;ARCHITECTURE BEHAV OF tiao ISSIGNAL A: STD_LOGIC_VECTOR (3 DOWNTO 0);BEGINPROCESS(K1,K2)BEGINIF K1'EVENT AND K1='1' THENA<=A+1;IF A=4 THENA<="0000"END IF;END IF;CASE A ISWHEN "0000"=>TL<=CLK;YO<=TI;NO<=YI;NO1<=NI; - 模式0正常计时 L1<='0'L2<='0'L3<='0'L4<='0' WHEN "0001"=>TL<=K2;YO<='0'NO<='0'NO1<='0' -选通日模块，调日；第1个灯亮 L1<='1'L2<='0'L3<='0'L4<='0' WHEN "0010"=>TL<='0'YO<=K2;NO<='0'NO1<='0' -选通月模块，调月；第2个灯亮 L1<='0'L2<='1'L3<='0'L4<='0' WHEN "0011"=>TL<='0'YO<='0'NO<=K2;NO1<='0' -选通年低位模块，调年低位；第3个灯亮 L1<='0'L2<='0'L3<='1'L4<='0'WHEN "0100"=>TL<='0'YO<='0'NO<='0'NO1<=K2; -选通年高位模块，调年高位；第4个灯亮 L1<='0'L2<='0'L3<='0'L4<='1' WHEN OTHERS=>NULL;END CASE;END PROCESS;END;仿真7·D7程序七段数码管（陈泽东）library ieee;use ieee.std_logic_1164.all;entity d7 isport(d0:in std_logic_vector(3 downto 0);c:out std_logic_vector(6 downto 0);end;architecture arc_d7 of d7 issignal din:std_logic_vector(3 downto 0);signal dout:std_logic_vector(6 downto 0);begindin<=d0;process(din)begincase din iswhen"0000"=>dout<="1111110" -7EH(显示0）when"0001"=>dout<="0110000" -30H(显示1）when"0010"=>dout<="1101101" -6DH(显示2）when"0011"=>dout<="1111001" -79H(显示3）when"0100"=>dout<="0110011" -33H(显示4）when"0101"=>dout<="1011011" -5BH(显示5）when"0110"=>dout<="1011111" -5FH(显示6）when"0111"=>dout<="1110000" -70H(显示7）when"1000"=>dout<="1111111" -7FH(显示8）when"1001"=>dout<="1111011" -7BH(显示9）when"1010"=>dout<="1111011" -77H(显示A）when"1011"=>dout<="0011111" -1FH(显示B）when"1100"=>dout<="1001110" -4EH(显示C）when"1101"=>dout<="0111101" -3DH(显示D）when"1110"=>dout<="1001111" -4FH(显示E）when"1111"=>dout<="1000111" -47H(显示F）when others=>dout<="1000111" -47H(显示F）end case;end process;c<=dout;end arc_d7;仿真8·De减震程序（李露）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity de isport(clk,key:in std_logic; dly_out:out std_logic);end de;architecture a of de issignal count:std_logic_vector(4 downto 0):="00000" -设置一个信号count的初始值为“00000”beginprocess(clk,key)begin if clk'event and clk='1' thenif key='1'thenif count=10 then count<=count; -来一个上升沿，且按键“key”按下，信号count为10时，输出信号，否则信号加1else count<=count+1;end if;if count=9 then dly_out<='1' -来一个上升沿，且按键“key”按下，信号count为9时，输出有效，否则输出无效else dly_out<='0'end if;else count<="00000"end if;end if;end process;end a;仿真9·Fenpin程序分频（李泽宙）ibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpin isport(clk:in std_logic; clk_out1:out std_logic; clk_out2:out std_logic; clk_out3:out std_logic);end;architecture one of fenpin issignal count1:integer range 0 to 35999999; -改X值signal clk_data1:std_logic;signal clk_data2:std_logic;signal count2:integer range 0 to 49999;signal clk_data3:std_logic;signal count3:integer range 0 to 994; -改X值beginprocess(clk,count1)begin if clk'event and clk='1' then if count1=35999999 then -X值决定分频倍数N,若要求160分频 count1<=0; clk_data1<=not clk_data1;-则X=N/2-1,这里X取9 else count1<=count1+1; end if;end if;clk_out1<=clk_data1;end process;process(clk,count2)begin if clk'event and clk='1' then if count2=49999 then -X值决定分频倍数N,若要求20分频 count2<=0; clk_data2<=not clk_data2;-则X=N/2-1,这里X取14else count2<=count2+1; end if;end if;clk_out2<=clk_data2;end process;process(clk,count3)begin if clk'event and clk='1' then if count3=994 then -X值决定分频倍数N,若要求20分频 count3<=0; clk_data3<=not clk_data3;-则X=N/2-1,这里X取14 else count3<=count3+1;end if;end if;clk_out3<=clk_data3;end process;end one;仿真10·wnl程序元件例化程序（李露，李泽宙，陈泽东）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wnl1 isport(clk,k1,k2:in std_logic;L1,L2,L3,L4:out std_logic;c:out std_logic_vector(6 downto 0);sel:out std_logic_vector(3 downto 0);dp:out std_logic;s:out std_logic_vector(3 downto 0);end wnl1;architecture one of wnl1 iscomponent tianPORT( a :IN STD_LOGIC; b:IN STD_LOGIC; -日计数器tian的元件声明 clk :IN STD_LOGIC; t1 :OUT STD_LOGIC_VECTOR (3 DOWNTO 0); t2 :OUT STD_LOGIC_VECTOR (7 DOWNTO 4); cout :OUT STD_LOGIC); end component; component yueport( clk:IN STD_LOGIC; -月计数器yue的元件声明 run:IN STD_LOGIC; cout:OUT STD_LOGIC; a :OUT STD_LOGIC; b: OUT STD_LOGIC; y1 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0); y2:OUT STD_LOGIC_VECTOR(7 DOWNTO 4) ; end component;component nianPORT( clk:IN STD_LOGIC; -年低位计数器nian的元件声明 n1,n2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); run,cout:OUT STD_LOGIC); end component;component nian2PORT( clk:IN STD_LOGIC; -年高位计数器nian2的元件声明 n3,n4:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); end component;component tiaoPORT( k1,k2 :IN STD_LOGIC; -校对模块tiao的元件声明 clk,ti,yi,ni :IN STD_LOGIC; tl,yo,no,no1:OUT STD_LOGIC; L1,L2,L3,L4 :OUT STD_LOGIC);end component;component fenpinport( clk:in std_logic; -分频模块fenpin的元件声明 clk_out1:out std_logic; clk_out2:out std_logic; clk_out3:out std_logic);end component;component seltimePORT(CLK1:IN STD_LOGIC; -扫描模块seltime的元件声明t1,t2,y1,y2,n1,n2,n3,n4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);daout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);dp:OUT STD_LOGIC;sel:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);end component;component d7PORT( d0:IN STD_LOGIC_VECTOR(3 DOWNTO 0); -译码器模块d7的元件声明c:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);end component;component de -减震模块de的元件声明port(clk,key:in std_logic; dly_out:out std_logic);end component;signal A :std_logic; -全局信号定义（用于内部连线）signal B: std_logic; -全局信号定义（用于内部连线） signal k1_out,k2_out: std_logic;signal day1,day2,mon1,mon2,year1,year2,year3,year4:std_logic_vector(3 downto 0); -全局信号定义（用于内部连线）signal c_out:std_logic_vector(6 downto 0); -全局信号定义（用于内部连线）signal d0_daout:std_logic_vector(3 downto 0); -全局信号定义（用于内部连线）signal temp,clk_cd,clk_cm,cout_td,cout_tm,cout_ty,clk_cy1,clk_cy2,clk_1,clk_2,clk_3:std_logic; -全局信号定义（用于内部连线）signal sel1:std_logic_vector(3 downto 0); -全局信号定义（用于内部连线）beginu1:tian port map(a=>A,b=>B, -u1：日计数器元件例化clk=>clk_cd,t1=>day1,t2=>day2,cout=>cout_td);u2:yue port map( clk=>clk_cm, -u2：月计数器元件例化 run=>temp, cout=>cout_tm, a=>A, b=>B, y1=>mon1, y2=>mon2);u3:nian port map( clk=>clk_cy1, -u3：年低位计数器元件例化 n1=>year1, n2=>year2, run=>temp, cout=>cout_ty);u4:nian2 port map( clk=>clk_cy2, -u4：年高位计数器元件例化 n3=>year3, n4=>year4);u5:tiao port map(K1=>k1_out, -u5：校对模块元件例化K2=>k2_out,CLK=>clk_1,ti=>cout_td,yi=>cout_tm,ni=>cout_ty,tl=>clk_cd,yo=>c