毕业设计（论文）2N次方广谱伪随机信号发生器及VHDL程序.doc

目 录第一章 前言·························································································· 1第二章 伪随机信号·············································································· 22.1 2n伪随机信号简介······································································· 2第三章 伪随机信号的时域分析·························································· 3第四章 伪随机信号发生器的VHDL描述········································ 84.1 用VHDL设计产生双频波··························································· 94.2 用VHDL设计产生三频波··························································· 94.3 主要构思及设计图····································································· 104.4 各种波的程序及波形································································· 14第五章 结论························································································ 30参考文献································································································ 31致谢······································································································· 32第一章 前言伪随机信号处理最早是从空间工程和军事等应用中发展起来的，至今已有40多年的历史。在这些应用中，重点主要集中在寻求某种信号格式以及信号处理技术，以保证信息的完整性，尤其在受到干扰攻击的时候更是如此。随着数字移动通信系统的发展、对定位系统需求的持续增长以及集成电路集成度的日益提高，伪随机信号处理作为一种可行的技术在民用和商用系统中得到越来越多的应用。伪随机序列通过设置数学乱源产生,它的伪随机性表现在预先的可确定性、可重复产生与处理,伪随机序列虽然不是真正的随机序列,但是当伪随机序列周期足够长时,伪随机序列具有随机序列的良好统计特性。伪随机序列广泛应用于密码学、扩频通讯、导航、集成电路的可测性设计等许多重要领域3。比如,密码学中伪随机序列通常被作为密钥,流密码中通过密钥流生成器产生性能优良的密钥流序列,使用该序列加密信息流得到密文序列,所以流密码的安全强度完全决定于密钥流序列的好坏。扩频通信中伪随机序列作为扩频码,利用伪随机序列码把基带信号的频谱进行扩展,形成相当带宽的低功率谱密度信号进行发射。使用不同的伪随机序列编码,不同通信用户可以在同一频段、同一时间工作,互不影响或影响极小。具有良好的伪随机特性的扩频编码对扩频通信及其技术的应用是非常重要的。基于伪随机序列具有的科学和社会价值, 对伪随机序列已经有了比较深入的研究。伪随机序列信号在雷达、遥控、遥测、通信加密和无线电测量系统领域有着广泛的应用。第二章 伪随机信号简介2n系列伪随机信号为中国工程院院士何继善发明和命名（He，jishan，1997，何继善，1998）。2n系列信号随着n的不同，在时间域上具有不同的波形，其频谱也相应的不同。但这些信号的频谱有一个共同的特点，就是它们的频谱在频率为2n共n个频率上大小基本相等，在这些频率上功率之和占了信号总平均功率的大部分，其余谐波含有的功率只占小部分，2n系列伪随机信号的名称也因此得来。单个伪随机信号根据n的取值命名为伪随机n频波。例如，当n取值为3、5、7、11时，将所对应的伪随机信号命名为伪随机三频波、伪随机五频波、伪随机七频波、伪随机十一频波。因此，2n系列伪随机信号是指无数个满足上述特点的信号的集合，伪随机n频波指的是2n系列伪随机信号的一个具体信号。2n系列伪随机信号的n频波电流含有n个主频，它是一种组合波，所包含的n个主频的频比固定为2，因此只要设计出一个n频波波形，以不同频率的时钟激励，便可得到频点不同的n频波伪随机信号，且频点可以任意加密。正因为2n系列伪随机信号具备了以上特点，在勘探，检测等领域得到应用，相信随着2n系列伪随机信号理论发展的越来越成熟，将在更多领域得到更广泛的应用。第三章 伪随机多频信号的时域分析3把2n系列伪随机信号作为周期信号分析，将伪随机n频波分解成若干分段连续函数的叠加。当n的取值不是无穷大时，可以对伪随机n频波进行傅立叶级数分解。得到2n系列伪随机信号波形解析式：用表示伪随机n频波，在周期内可以表示为： (3-1)式中表示区间数，为整数。式（3-1）表明，伪随机n频波振幅的绝对值不变，每个小区间的长度为T/2n的整数倍。伪随机三频波在周期内有4个区间，表达式为式（3-2）： (3-2) 伪随机五频波在内的表达式为： (3-3)伪随机n频波是奇函数，只要求出它在半个周期内的表达式，就可以知道它在整个周期上的表达式。在式（3-3）中，只给出伪随机五频波在内的表达式。对于伪随机n频波，n的取值越大，波形中的间断点就越多。例如，伪随机三频波有4个间断点，伪随机五频波有12个间断点，伪随机七频波有40个间断点，伪随机九频波有140个间断点。图3-1伪随机双频波一个周期的时域波形及其频谱图3-1为伪随机双频波一个周期的时域波形及其频谱。图3-2至图3-8分别为周期为1秒、振幅为1的伪随机三频波、伪随机五频波、伪随机四进制三频波、伪随机七频波、伪随机九频波、伪随机十一频波和伪随机十三频波的一个周期的波形及其频谱。从波形中可以看出，随着n的增大，波形越来越复杂，波形振幅的变化也越来越快，这意味信号的带宽也越来越大。图3-2 伪随机三频波(A=1, T=1s)时域波形及其频谱图3-3 伪随机五频波(A=1, T=1s) 时域波形及其频谱图3-4 伪随机四进制三频波(A=1, T=1s) 时域波形及其频谱图3-5 伪随机七频波(A=1, T=1s) 时域波形及其频谱图2-6 伪随机九频波(A=1, T=1s) 时域波形及其频谱图3-7 伪随机十一频波(A=1, T=1s) 时域波形及其频谱图3-8 伪随机十三频波(A=1, T=1s) 时域波形及其频谱第四章 伪随机信号发生器的VHDL描述4.1 用VHDL设计产生双频波 用VHDL可以设计产生任意波形。下面以伪随机双频波VHDL源程序为例，来说明如何用状态机产生波形的。 图 4-1 一个周期双频波形的二进制序列先将双频波波形按状态进行二进制编码，如图 3-2所示，导通为1，截止为0，两个控制信号在一个周期内共有26个状态。将这26个状态定义成名为STATES的枚举数据类型。用ss表示正向导通控制信号，用ss0表示方向导通控制信号。如在WAVEGEN进程中所描述的，状态机在时钟的激励下，26个状态依次转换，并同时输出ss和ss0对应的编码。第26个状态的下一个状态是第一个状态，这样就连续不断地产生双频波波形5。4.2 用VHDL设计产生三频波及其它波形从三频波一个周期0，T）的波形解析式（3-2）式中可以看出，波形可以分为四个期间，每个期间的长度是最小期间长度的T/23为基本单位对这一个周期的波形重新分割并进行2的进制编码，同样的，1表示导通，0表示截止12，则如图4-2所示。图 4-2 三频波波形二进制编码序列三频波的一个周期波形可以定义为23个状态，且反向导通编码是正向导通编码的反码。同理，五频波的一个周期波形可以定义为25个状态，七频波共有27个状态，一十三频波共有213个状态1。图 4-3 二进制五频波波形编码序列4.3 主要构思及设计图1 应用VHDL中的状态机描述单个的波形，通过Quartus 对其进行编译仿真，即可得到想要的伪随机波形。单个的波形VHDL编程及波形产生完成后，对相应的程序进行封装，得到相应的元器件，然后在Quartus 中建立一个pdf文件，通过一个数字选通器把所有的波形元器件连接起来。通过编译适配之后，只需输入相应的数字，通过仿真即可得到想要的伪随机波形，十分简便。具体结构图如图4-4：图4-4 整体设计图 图4-5 整体电路图图4-6 整体设计图的状态图Flow StatusSuccessful - Thu May 13 22:41:42 2010Quartus II Version8.1 Build 163 10/28/2008 SJ Full VersionRevision NamezztTop-level Entity NamezztFamilyCyclone IIDeviceEP2C5T144C8Timing ModelsFinalMet timing requirementsYesTotal logic elements4 / 4,608 ( < 1 % ) Total combinational functions4 / 4,608 ( < 1 % ) Dedicated logic registers4 / 4,608 ( < 1 % )Total registers4Total pins4 / 89 ( 4 % )Total virtual pins0Total memory bits0 / 119,808 ( 0 % )Embedded Multiplier 9-bit elements0 / 26 ( 0 % )Total PLLs0 / 2 ( 0 % )由以上综合分析报告可以看出运行该工程占用的芯片资源非常少，对硬件的要求不高，使得该设计的FPGA实现变得容易。再查看时序分析，可以看到产生波形的时钟周期（Clock period）为2.91ns，频率（Frequency）为340.02Mhz，速度非常快。该设计的上述优势为伪随机波的实际开发应用及推广提供了便宜。4.4 各种波的源程序及波形本设计适配以后，经时序仿真检验，完全达到设计要求，波形选择和频率选择控制灵活。以下为各种伪随机波的原程序、时序仿真的波形、电路图及状态图：双频波的VHDL源程序、时序图及电路图： Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity pinbo_2 is Port( Clk,clk1,reset ,en:in std_logic; wave1: out std_logic; wave2: out std_logic); End ; Architecture qsg of pinbo_2 is Type states is (st0, st1, st2, st3, st4, st5, st6, st7, st8, st9, st10, st11, st12, st13, st14, st15, st16, st17, st18, st19, st20, st21, st22, st23, st24, st25 );Signal ss,ss0:std_logic; Begin REG: process(clk1,reset,en) Variable c_state:states; Variable n_state:states;Begin If reset= '1' then C_state:=st0; ss<='0' ss0<='0' Elsif clk1'event and clk1='1' then if en='1' then Case c_state is When st0=> ss<='0' ss0<='0' n_state:=st1; When st1=> ss<='1' ss0<='0' n_state:=st2; When st2=> ss<='0' ss0<='0' n_state:=st3; When st3=> ss<='1' ss0<='0' n_state:=st4; When st4=> ss<='0' ss0<='0' n_state:=st5; When st5=> ss<='1' ss0<='0' n_state:=st6; When st6=> ss<='0' ss0<='0' n_state:=st7; When st7=> ss<='1' ss0<='0' n_state:=st8; When st8=> ss<='0' ss0<='0' n_state:=st9; When st9=> ss<='1' ss0<='0' n_state:=st10; When st10=> ss<='0' ss0<='0' n_state:=st11; When st11=> ss<='1' ss0<='0' n_state:=st12; When st12=> ss<='0' ss0<='0' n_state:=st13; When st13=> ss<='0' ss0<='0' n_state:=st14; When st14=> ss<='0' ss0<='1' n_state:=st15; When st15=> ss<='0' ss0<='0' n_state:=st16; When st16=> ss<='0' ss0<='1' n_state:=st17; When st17=> ss<='0' ss0<='0' n_state:=st18; When st18=> ss<='0' ss0<='1' n_state:=st19; When st19=> ss<='0' ss0<='0' n_state:=st20; When st20=> ss<='0' ss0<='1' n_state:=st21; When st21=> ss<='0' ss0<='0' n_state:=st22; When st22=> ss<='0' ss0<='1' n_state:=st23; When st23=> ss<='0' ss0<='0' n_state:=st24; When st24=> ss<='0' ss0<='1' n_state:=st25; When st25=> ss<='0' ss0<='0' n_state:=st0; When others => null; End case; C_state:=n_state;end if;End if;End process;COM : process( clk, reset, ss, ss0,en)Begin If reset='1' then wave1<='0' wave2<='0' Elsif clk'event and clk='1' then if en ='1' then wave1<=ss; wave2<=ss0; End if; end if;End process;End; 通过对上面的程序适配仿真即可得到双频波的时序波形、电路图和状态图。如图4-7, 4-8，4-9所示：图4-7 双频波波形双频波有1、0、-1三个状态，因为quartus 只能表示0、1两个种状态值，所以必须把双频波拆开成两部分显示出来，如图4-3所示， wave1为双频波的正半部分，wave2为双频波的负半部分。其它的波只有0、1两个状态，都能直接用quartus 直接表示出来。图4-8 双频波发生器的电路图图4-9 双频波的状态图三频波的VHDL源程序：Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity pinbo_3 is Port( clk,reset :in std_logic; wave : out std_logic); End ;Architecture qsg of pinbo_3 is subtype state is integer range 0 to 7; Signal ss:std_logic;Begin process( clk, reset) variable c_state:state; Begin If reset= '1' then ss<='0' c_state:=0; Elsif clk='1' and clk'event then Case c_state is When 0 to 2 => ss <='1' When 3 => ss <='0' When 4 => ss <='1' When 5 to 7 => ss <='0' when others => null; End case; C_state:=c_state + 1; End if; wave <=ss; end process;End ;通过对上面的程序适配仿真即可得到三频波的时序波形和电路图。如图4-10,4-11所示： 图4-10 2n进制三频波图4-11 2n进制三频波发生器电路图下面是产生五频波的VHDL源程序：Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all;Entity pinbo_5 is Port( clk,reset :in std_logic;wave : out std_logic);End ;Architecture qsg of pinbo_5 is subtype state is integer range 0 to 31; Signal ss:std_logic;Begin process( clk, reset)variable c_state:state;BeginIf reset= '1' thenss<='0' c_state:=0;Elsif clk='1' and clk'event thenCase c_state is When 0 to 6 => ss <='1' When 7 => ss <='0' When 8 to 10 => ss <='1' When 11 => ss <='0' When 12 => ss <='1' When 13 to 15 => ss <='0' When 16 to 18 => ss <='1' When 19 => ss <='0' When 20 => ss <='1' When 21 to 23 => ss <='0' When 24 => ss <='1' When 25 to 31 => ss <='0' when others => null; End case; C_state:=c_state + 1; End if; wave <=ss; end process;End ;通过对上面的程序适配仿真即可得到五频波的时序波形和电路图。如图4-12,4-13所示：图4-12 2n进制五频波图4-13 2n进制五频波发生器电路图四进制三频波的VHDL源程序：Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity pinbo_6 is Port( clk,reset :in std_logic; wave : out std_logic);End ;Architecture qsg of pinbo_6 is subtype state is integer range 0 to 63; Signal ss:std_logic; Begin process( clk, reset) variable c_state:state; Begin If reset= '1' then ss<='0' c_state:=0; Elsif clk='1' and clk'event then Case c_state is When 0 to 9 => ss <='1' When 10 to 11 => ss <='0' When 12 to 13 => ss <='1' When 14 to 15 => ss <='0' When 16 to 25 => ss <='1' When 26 to 27 => ss <='0' When 28 to 29 => ss <='1' When 30 to 31 => ss <='0' When 32 to 33 => ss <='1' When 34 to 35 => ss <='0' When 36 to 37 => ss <='1' When 38 to 47 => ss <='0' When 48 to 49 => ss <='1' When 50 to 51 => ss <='0' When 52 to 53 => ss <='1' When 54 to 63 => ss <='0' when others => null; End case; C_state:=c_state + 1; End if; wave <=ss; end process;End ;通过对上面的程序适配仿真即可得到四进制三频波的时序波形，电路图和状态图。如图4-14, 4-15，4-16所示：图4-14 4进制三频波图4-15 4进制三频波发生器电路图图4-16 4进制三频波状态图下面是产生七频波的VHDL源程序：Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity pinbo_7 is Port( clk,reset :in std_logic; wave : out std_logic); End ; Architecture qsg of pinbo_7 is subtype state is integer range 0 to 127; Signal ss:std_logic;Begin process( clk, reset) variable c_state:state; Begin If reset= '1' then ss<='0' c_state:=0; Elsif clk='1' and clk'event then Case c_state is When 0 to 14 => ss <='1' When 15 => ss <='0' When 16 to 22 => ss <='1' When 23 => ss <='0' When 24 to 26 => ss <='1' When 27 => ss <='0' When 28 => ss <='1' When 29 to 31 => ss <='0' When 32 to 38 => ss <='1' When 39 => ss <='0' When 40 to 46 => ss <='1' When 47 => ss <='0' When 48 => ss <='1' When 49 to 51 => ss <='0' When 52 to 54 => ss <='1' When 55 => ss <='0' When 56 => ss <='1' When 57 to 59 => ss <='0' When 60 => ss <='1' When 61 to 63 => ss <='0' When 64 to 70 => ss <='1' When 71 => ss <='0' When 72 to 74 => ss <='1' When 75 => ss <='0' When 76 => ss <='1' When 77 to 79 => ss <='0' When 80 to 82 => ss <='1' When 83 => ss <='0' When 84 => ss <='0' When 85 to 87 => ss <='1' When 88 => ss <='0' When 89 to 95 => ss <='1' When 96 to 97 => ss <='0' When 99 => ss <='1' When 100 => ss <='0' When 101 to 103 => ss <='1' When 104 => ss <='0' When 105 to 111 => ss <='0' When 112 => ss <='0' When 113 to 127 => ss <='0' when others => null; End case; C_state:=c_state + 1; End if; wave <=ss; end process;End ;通过对以上的程序的适配仿真即可得到七频波的时序波形和电路图。如图4-17,4-18所示： 图4-17 2n进制七频波图4-18 2n进制七频波发生器电路图选通器源程序： library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity XT isport( clk ,en,reset,wave1,wave3,wave5,wave6,wave7: in std_logic;shuru:in std_logic_vector(3 downto 0);wave: out std_logic);end;architecture qsg of XT is Signal ss:std_logic;beginprocess(clk,shuru,en,reset)beginIf reset= '1' thenss<='0' Elsif clk'event and clk='1' thenif en='1' then case shuru iswhen "0000" => ss <= '0'when "0001" => ss <= wave1;when "0010" => ss <= wave3;when "0011" => ss <= '0'when "0100" => ss <= wave5;when "0101" => ss <= wave6;when "0110" => ss <= wave7;when "0111" => ss <= '0'when "1000" => ss <= '0'when "1001" => ss <= '0'when "1010" => ss <= '0'when "1011" => ss <= '0'when "1100" => ss <= '0'when "1101" => ss <= '0'when "1110" => ss <= '0'when others => null; end case;end if;end if;wave <= ss;end process;end ; 图4-19 选通器电路图第五章 结论何继善院士发明和命名的2n系列伪随机信号，由于其带宽可控，能量主要集中在2n进制的几个频点上，是电法勘探的理想场源。用它取代人工场源频率域电法勘探中的方波或类似方波信号为场源，可克服变频法和奇次谐波法工作效率低，观测精度不高的缺点。目前，2N均匀广谱伪随机信号在许多领域已经得到应用，特别是在地球勘探领域得到重视。随着微电子技术计算机技术的发展，特别是复杂可编程逻辑器件CPLD及其开发软件日新月异的进步，2N均匀广谱伪随机信号的广泛应用将毋庸置疑。参 考 文 献1 罗维宾 硕士毕业论文 中南大学 20042 何继善.可控源音频大地电磁法.长沙:中南工业大学出版社,1990.3 何继善 金属矿探矿技术现状及“十一五”工作建议4 潘松 黄继业 EDA技术实用教程 科学出版社 20065 赵世廉 DSP原来及应用 北京航空航天大学出版社 20076 江国强 SOPC技术与应用 机械工业出版社 20067 潘松 黄继业 EDA技术与VHDL 清华大学出版社 20078 焦素敏 EDA技术与应用 清华大学出版社 20079 潘松，黄继业，曾毓. SoPC技术实用教程. 清华大学出版社，200510 李洋