数字集成电路分析与设计 第六章答案.docx
数字集成电路分析与设计 第六章答案CHAPTER 6 P6.1. The on-resistance of a unit-sized NMOS device. LINEAR | SATURATION On-resistance of a unit-sized NMOS device252015105000.20.40.60.811.2VDSThe average on-resistance is approximately 15k. The expression for the average resistance value between VDD and VDD2. RON(VDD)+RON(VDDRON=23VDD=24ID,sat4WvsatCox(VGS-VT)23VDD(VGS-VT+ECNLN)=VDS(VDD)IDS(VDD)(VDD2)+IVDDDS(2)=2VDSVDDID,sat+2VDDID,sat2P6.2. Since the signal must go around the ring twice for one oscillation, the period is : tTOT=N(tPLH+tPHL)=N(RPCLOAD+RNCLOAD)=N(RP+RN)(CWW)æLLö=NçREQP+REQN÷(Cg+Ceff)(WP+WN)WPWNøè1æö=7ç(30´103)+(12.5´103)÷(2+1)(10-15)(0.3)2èø=7(27.5´103)(3´10-15)(0.3)=173psf=1tTOT=1=5.77GHz Independent of inverter size. 173psP6.3. SPICE. P6.4. The self-capacitance in these cases are the capacitances that will make the transition from 0 to VDD or vice versa. a. In this case, all the internal nodes will be charged so the self-capacitance is : CSELF=Ceff(2W+2W+3W+3W+3W)=13CeffW b. In this case, all the internal nodes but the one above the bottom NMOS transistor will be charged: CSELF=Ceff(2W+2W+3W+3W)=10CeffW c. If we assume a worst-case scenario, this node will be charged up to VDD from 0. CSELF=Ceff(2W+2W+3W+3W+3W)=13CeffW d. The node above the bottom-most NMOS transistor has already been discharged. CSELF=Ceff(2W+2W+3W+3W)=10CeffW P6.5. SPICE P6.6. For optimum sizing given four inverters. PE=ÕLE´FO=(1)(1)(1)(1)(1200)=1200SE=NPE=41200=5.89LE´COUT1(1200)=203.89SE5.89LE´C41(203.89)C3=34.64SE5.89LE´C31(34.64)C2=5.89SE5.89LE´C21(5.89)C1=1SE5.89C4=D=å(LE´FO+P)=å(SE+P)=4(5.89+0.5)=25.511N4For the number of devices for optimum delay: SE=NPESEN=PElogSEN=logPENlogSE=logPEN=logPElog1200=5.11logSElog4Setting N=5 gives: SE=NPE=51200=4.12C5=C4=C3=C2=C1=LE´COUT1(1200)=290.63SE4.12LE´C51(290.63)=70.39SE4.12LE´C41(70.39)=17.05SE4.12LE´C31(17.05)=4.12SE4.12LE´C21(4.12)=1SE4.12N151D=å(LE´FO+P)=å(SE+P)=4(4.12+0.5)=18.5P6.7. Solution for NAND3 2W2W3W3W3W2W4W4W6W6W6W4WFor the first NAND3, LE=5W/3W=5/3. For the second NAND3, the delay is not the same as the basic inverter. So use the more general formula: LEnand3=10W´R/2=5/3 Same as the first case. 3WRP6.8. a. For equal rise and fall time, we double the sizes of the transistors which leads to: LE=3=1 3b. For the pseudo-NMOS, we must first calculate the currents, which are different for pull-up and pull-down in the case of a pseudo-NMOS. For the case of the pull-up, only the PMOS is charging the output, for equal delays, we double the size of the PMOS and NMOS to obtain: LE=2 3P6.9. 5a. LE= 35b. LE= 382c. LER=,LEF= 334d. LER=,LEF=2 3P6.10. a. LER=b. LEF= 83531stgate 2ndgate P6.11. æ4öæ5öPE=ÕLE´FO=(1)ç÷ç÷(1)(1000)=2222è3øè3øSE=NPE=42222=6.87LE´COUT(1)(1000)=145.65SE6.87)(145.65)=35.36LE´C4(5C3=3SE6.87)(35.36)=6.87LE´C3(4C2=3SE6.87LE´C2(1)(6.87)C1=1SE6.87C4=D=å(SE+PN)=å(SE+PN)=4(6.87)+0.5+1+1.5+0.5=3111N4P6.12. æ5öæ4öæ6öPE=ÕLE´FO´BE=ç÷ç÷ç÷(4)(1000)=17778è3øè3øè3øSE=NPE=417778=11.55C4=C3=C2=C1=)(1000)(1)=173.21LE´COUT´BE(6=3SE11.55)(173.21)(1)=25LE´C4´BE(5=3SE11.55)(25)(4)=11.55LE´C3´BE(4=3SE11.55LE´C2´BE(1)(11.55)(1)=1SE11.55N141D=å(SE+PN)=å(SE+PN)=4(11.55)+0.5+1+1.5+2=51.2P6.13. æ4öæ5öæ7öPE=ÕLE´FO´BE=(1)ç÷ç÷ç÷(2)(2)(4)(8000)=667303è3øè3øè3øSE=NPE=5663703=14.6)(8000)(1)=1095.8LE´COUT´BE(6C5=3SE14.6)(1095)(1)=175.1LE´C5´BE(7C4=3SE14.6æ4öæ5öPE=ÕLE´FO´BE=(1)ç÷ç÷(2)(4´175.1+500)=5335è3øè3øSE=NPE=35335=17.47)(1200)(1)=114.3LE´C4´BE(5C3=3SE17.5æ4ö÷(114.3)(2)LE´C3´BEç3C2=èø=17.5SE17.5LE´C2´BE(1)(17.5)(1)C1=1SE17.5D=å(SE+PN)=å(SE+PN)=3(17.5)+2(14.6)+0.5+1+1.5+2.25+2=88.911N5To minimize the delay, a estimate of the number of needed stages can be performed : SE=NPE logPElog663704N=9.6»10logSElog4The additional stages can be implemented as inverters attached at the input. P6.14. Consider the following situations : VddVinVoutCLVinVddVoutCLOutput high-to-lowOutput low-to-highIn the first case, the output is making a transition from high to low. The next inverter (not shown) has the PMOS in the cutoff region and the NMOS in the linear region. In these regions, the input capacitance of the next gate can be computed as follows: PMOS: CGP=Cg x 2W x (1/2) NMOS: CGN=Cg x W For the output low-to-high transition, we have the PMOS linear and the NMOS cutoff: PMOS: CGP=Cg x 2W NMOS: CGN=Cg x W (1/2) Clearly, the second case has a larger total capacitance and hence a larger effective Cg. P6.15. For this problem we examine ramp inputs as compared to step inputs. In both cases below, the transistors being driven enter the linear region and experience larger gate capacitances than the step input case. Therefore, Cg is always larger for ramp inputs. VddVinVDD-|VTP|VddVinVDD-|VTP|VoutVoutCLCLVTNVTNpositive-going input rampnegative-going input rampP6.16. The FO4 delay for 0.18um is approximately 75ps. For 0.13um it is 55ps. Therefore, the constant for the equation is roughly 420ps/um.
