Verilog工程文件类型.docx
Verilog工程文件类型File Type AHDL Include File ATOM Netlist File Block Design File Block Symbol File BSDL file Chain Description File Comma-Separated Value File Component Declaration File Compressed Vector Waveform. File Conversion Setup File Cross-Reference File database files DSP Block Region File EDIF Input File Global Clock File Graphic Design File HardCopy files Hexadecimal (Intel-Format) File Hexadecimal (Intel-Format) Output FileHSPICE Simulation Deck File HTML-Format Report File I/O Pin State File IBIS Output File In System Configuration File Jam Byte Code File Jam File JTAG Indirect Configuration File Library Mapping File License File Logic Analyzer Interface File Memory Initialization File Memory Map File PartMiner edaXML-Format File Pin-Out File Extension .inc .atm .bdf .bsf .bsd .cdf .csv .cmp .cvwf .cof .xrf .cdb, .hdb, .rdb, .tdb .macr .edf, .edif, .edn .gclk .gdf .datasheet, .sdo, .tcl, .vo .hex .hexout .sp .htm .ips .ibs .isc .jbc .jam .jic .lmf license.dat .lai .mif .map .xml .pin placement constraints file Programmer Object File programming files QMSG File Quartus II Archive File Quartus II Archive Log File Quartus User-Defined Device File Quartus II Default Settings File Quartus II Exported Partition FileQuartus II Project File Quartus II Settings File Quartus II Workspace File RAM Initialization File Raw Binary File Raw Programming Data File Routing Constraints File Signal Activity File SignalTap II File Simulator Channel File SRAM Object File Standard Delay Format Output File Symbol File Synopsys Design Constraints File Tab-Separated Value File Tabular Text File Tcl Script. File Text Design File Text-Format Report File Text-Format Timing Summary File Timing Analysis Output File Token File Vector File Vector Table Output File vector source files Vector Waveform. File Verilog Design File .apc .pof .cdf, .cof .qmsg .qar .qarlog .qud .qdf .qxp .qpf .qsf .qws .rif .rbf .rpd .rcf .saf .stp .scf .sof .sdo .sym .sdc .txt .ttf .tcl .tdf .rpt .tan.summary .tao ted.tok .vec .tbl .tbl, .vwf, .vec .vwf .v, .vh, .verilog, .vlg Verilog Output File Verilog Quartus Mapping File Verilog Test Bench File Value Change Dump File version-compatible database files VHDL Design File VHDL Output File VHDL Test Bench File XML files waveform. files 上面这些文件可以分为五类: .vo .vqm .vt .vcd .atm, .hdbx, .rcf, .xml .vhd, .vhdl .vho .vht .cof, .stp, .xml .scf, .stp, .tbl, .vec, .vwf 1.编译必需的文件:设计文件、存储器初始化文件、配置文件、工程文件。 2.编译过程中生成的中间文件 3.编译结束后生成的报告文件 4.根据个人使用习惯生成的界面配置文件 5.编程文件 上面分类中的第一类文件是一定要保留的;第二类文件在编译过程中会根据第一类文件生成,不需要保留;第三类文件会根据第一类文件的改变而变化,反映了编译后的结果,可以视需要保留;第四类文件保存了个人使用偏好,也可以视需要保留;第五类文件是编译的结果,一定要保留。 在使用版本控制工具时,我通常保留第一类、第三类和第五类文件。但是第三类文件通常很少被反复使用。 所以,为了维护一个最小工程,第一类和第五类文件是一定要保留的。 此外,当一个项目的设置内容需要转移给另一个项目时,例如引脚分配信息,需要转移.tcl文件而不是.qsf文件。.tcl文件与.qsf