max7000系列设计必备.ppt

,1,MAX 7000Programmable LogicDevice Family,November 2001,ver.6.3,Data Sheet,Features.,High-performance,EEPROM-based programmable logic devices(PLDs)based on second-generation MAX architecture,5.0-V in-system programmability(ISP)through the built-inIEEE Std.1149.1 Joint Test Action Group(JTAG)interface available inMAX 7000S devicesISP circuitry compatible with IEEE Std.1532Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000SdevicesBuilt-in JTAG boundary-scan test(BST)circuitry in MAX 7000Sdevices with 128 or more macrocellsComplete EPLD family with logic densities ranging from 600 to5,000 usable gates(see Tables 1 and 2)5-ns pin-to-pin logic delays with up to 175.4-MHz counterfrequencies(including interconnect)PCI-compliant devices available,f,For information on in-system programmable 3.3-V MAX 7000A or 2.5-VMAX 7000B devices,see the MAX 7000A Programmable Logic Device FamilyData Sheet or the MAX 7000B Programmable Logic Device Family DataSheet.,Table 1.MAX 7000 Device Features,Feature,EPM7032,EPM7064,EPM7096,EPM7128E,EPM7160E,EPM7192E,EPM7256E,Usable,600,1,250,1,800,2,500,3,200,3,750,5,000,gates,Macrocells,32,64,96,128,160,192,256,Logic array,2,4,6,8,10,12,16,blocks,Maximum,36,68,76,100,104,124,164,user I/O pins,tPD(ns),6,6,7.5,7.5,10,12,12,tSU(ns),5,5,6,6,7,7,7,tFSU(ns),2.5,2.5,3,3,3,3,3,tCO1(ns),4,4,4.5,4.5,5,6,6,fCNT(MHz),151.5,151.5,125.0,125.0,100.0,90.9,90.9,Altera Corporation,A-DS-M7000-6.3,I,I,I,I,I,I,I,I,I,2,MAX 7000 Programmable Logic Device Family Data Sheet,Table 2.MAX 7000S Device Features,Feature,EPM7032S,EPM7064S,EPM7128S,EPM7160S,EPM7192S,EPM7256S,Usable gates,600,1,250,2,500,3,200,3,750,5,000,Macrocells,32,64,128,160,192,256,Logic array,2,4,8,10,12,16,blocks,Maximum,36,68,100,104,124,164,user I/O pins,tPD(ns),5,5,6,6,7.5,7.5,tSU(ns),2.9,2.9,3.4,3.4,4.1,3.9,tFSU(ns),2.5,2.5,2.5,2.5,3,3,tCO1(ns),3.2,3.2,4,3.9,4.7,4.7,fCNT(MHz),175.4,175.4,147.1,149.3,125.0,128.2,.and MoreFeatures,Open-drain output option in MAX 7000S devicesProgrammable macrocell flipflops with individual clear,preset,clock,and clock enable controls,Programmable power-saving mode for a reduction of over 50%ineach macrocellConfigurable expander product-term distribution,allowing up to32 product terms per macrocell44 to 208 pins available in plastic J-lead chip carrier(PLCC),ceramicpin-grid array(PGA),plastic quad flat pack(PQFP),power quad flatpack(RQFP),and 1.0-mm thin quad flat pack(TQFP)packagesProgrammable security bit for protection of proprietary designs3.3-V or 5.0-V operationMultiVoltTM I/O interface operation,allowing devices tointerface with 3.3-V or 5.0-V devices(MultiVolt I/O operation isnot available in 44-pin packages)Pin compatible with low-voltage MAX 7000A and MAX 7000BdevicesEnhanced features available in MAX 7000E and MAX 7000S devicesSix pin-or logic-driven output enable signalsTwo global clock signals with optional inversionEnhanced interconnect resources for improved routabilityFast input setup times provided by a dedicated path from I/Opin to macrocell registersProgrammable output slew-rate controlSoftware design support and automatic place-and-route provided byAlteras development system for Windows-based PCs and SunSPARCstation,and HP 9000 Series 700/800 workstationsAltera Corporation,I,I,3,MAX 7000 Programmable Logic Device Family Data SheetAdditional design entry and simulation support provided by EDIF2 0 0 and 3 0 0 netlist files,library of parameterized modules(LPM),Verilog HDL,VHDL,and other interfaces to popular EDA tools frommanufacturers such as Cadence,Exemplar Logic,Mentor Graphics,OrCAD,Synopsys,and VeriBestProgramming supportAlteras Master Programming Unit(MPU)and programminghardware from third-party manufacturers program allMAX 7000 devicesThe BitBlasterTM serial download cable,ByteBlasterMVTMparallel port download cable,and MasterBlasterTMserial/universal serial bus(USB)download cable program MAX7000S devices,GeneralDescription,The MAX 7000 family of high-density,high-performance PLDs is basedon Alteras second-generation MAX architecture.Fabricated withadvanced CMOS technology,the EEPROM-based MAX 7000 family,provides 600 to 5,000 usable gates,ISP,pin-to-pin delays as fast as 5 ns,and counter speeds of up to 175.4 MHz.MAX 7000S devices in the-5,-6,-7,and-10 speed grades as well as MAX 7000 and MAX 7000E devices in-5,-6,-7,-10P,and-12P speed grades comply with the PCI Special InterestGroup(PCI SIG)PCI Local Bus Specification,Revision 2.2.See Table 3for available speed grades.,Table 3.MAX 7000 Speed Grades,Device,Speed Grade,-5,-6,-7,-10P,-10,-12P,-12,-15,-15T,-20,EPM7032,v,v,v,v,v,v,EPM7032S,v,v,v,v,EPM7064,v,v,v,v,v,EPM7064S,v,v,v,v,EPM7096,v,v,v,v,EPM7128E,v,v,v,v,v,v,EPM7128S,v,v,v,v,EPM7160E,v,v,v,v,v,EPM7160S,v,v,v,v,EPM7192E,v,v,v,v,EPM7192S,v,v,v,EPM7256E,v,v,v,v,EPM7256S,v,v,v,Altera Corporation,(1),(2),4,MAX 7000 Programmable Logic Device Family Data Sheet,The MAX 7000E devicesincluding the EPM7128E,EPM7160E,EPM7192E,and EPM7256E deviceshave several enhanced features:additional global clocking,additional output enable controls,enhancedinterconnect resources,fast input registers,and a programmable slewrate.In-system programmable MAX 7000 devicescalled MAX 7000Sdevicesinclude the EPM7032S,EPM7064S,EPM7128S,EPM7160S,EPM7192S,and EPM7256S devices.MAX 7000S devices have theenhanced features of MAX 7000E devices as well as JTAG BST circuitry indevices with 128 or more macrocells,ISP,and an open-drain outputoption.See Table 4.Table 4.MAX 7000 Device Features,FeatureISP via JTAG interfaceJTAG BST circuitryOpen-drain output optionFast input registersSix global output enablesTwo global clocksSlew-rate controlMultiVolt interface(2)Programmable registerParallel expandersShared expandersPower-saving modeSecurity bitPCI-compliant devices available,EPM7032EPM7064EPM7096vvvvvvv,AllMAX 7000EDevicesvvvvvvvvvvv,AllMAX 7000SDevicesvv(1)vvvvvvvvvvvv,Notes:Available only in EPM7128S,EPM7160S,EPM7192S,and EPM7256S devices only.The MultiVolt I/O interface is not available in 44-pin packages.Altera Corporation,(1),(2),5,MAX 7000 Programmable Logic Device Family Data SheetThe MAX 7000 architecture supports 100%TTL emulation andhigh-density integration of SSI,MSI,and LSI logic functions.TheMAX 7000 architecture easily integrates multiple devices ranging fromPALs,GALs,and 22V10s to MACH and pLSI devices.MAX 7000 devicesare available in a wide range of packages,including PLCC,PGA,PQFP,RQFP,and TQFP packages.See Table 5.,Table 5.MAX 7000 Maximum User I/O Pins,Note(1),Device,44-,44-,44-,68-,84-100-100-,160-,160-,192-,208-,208-,Pin,Pin,Pin,Pin,Pin,Pin,Pin,Pin,Pin,Pin,Pin,Pin,EPM7032,PLCC PQFP TQFP PLCC PLCC PQFP TQFP363636,PQFP,PGA,PGA,PQFP,RQFP,EPM7032S,36,36,EPM7064,36,36,52,68,68,EPM7064S,36,36,68,68,EPM7096,52,64,76,EPM7128E,68,84,100,EPM7128S,68,84,84(2),100,EPM7160E,64,84,104,EPM7160S,64,84(2),104,EPM7192E,124,124,EPM7192S,124,EPM7256E,132(2),164,164,EPM7256S,164(2),164,Notes:,When the JTAG interface in MAX 7000S devices is used for either boundary-scan testing or for ISP,four I/O pins,become JTAG pins.,Perform a complete thermal analysis before committing a design to this device package.For more information,see,the Operating Requirements for Altera Devices Data Sheet.,MAX 7000 devices use CMOS EEPROM cells to implement logicfunctions.The user-configurable MAX 7000 architecture accommodates avariety of independent combinatorial and sequential logic functions.Thedevices can be reprogrammed for quick and efficient iterations duringdesign development and debug cycles,and can be programmed anderased up to 100 times.,Altera Corporation,I,I,I,I,6,MAX 7000 Programmable Logic Device Family Data Sheet,MAX 7000 devices contain from 32 to 256 macrocells that are combinedinto groups of 16 macrocells,called logic array blocks(LABs).Eachmacrocell has a programmable-AND/fixed-OR array and a configurableregister with independently programmable clock,clock enable,clear,andpreset functions.To build complex logic functions,each macrocell can besupplemented with both shareable expander product terms and high-speed parallel expander product terms to provide up to 32 product termsper macrocell.The MAX 7000 family provides programmable speed/poweroptimization.Speed-critical portions of a design can run at highspeed/full power,while the remaining portions run at reducedspeed/low power.This speed/power optimization feature enables thedesigner to configure one or more macrocells to operate at 50%or lowerpower while adding only a nominal timing delay.MAX 7000E andMAX 7000S devices also provide an option that reduces the slew rate ofthe output buffers,minimizing noise transients when non-speed-criticalsignals are switching.The output drivers of all MAX 7000 devices(except44-pin devices)can be set for either 3.3-V or 5.0-V operation,allowingMAX 7000 devices to be used in mixed-voltage systems.The MAX 7000 family is supported byAltera development systems,whichare integrated packages that offer schematic,textincluding VHDL,Verilog HDL,and the Altera Hardware Description Language(AHDL)and waveform design entry,compilation and logic synthesis,simulationand timing analysis,and device programming.The software providesEDIF 2 0 0 and 3 0 0,LPM,VHDL,Verilog HDL,and other interfaces foradditional design entry and simulation support from other industry-standard PC-and UNIX-workstation-based EDA tools.The software runson Windows-based PCs,as well as Sun SPARCstation,and HP 9000 Series700/800 workstations.,f,For more information on development tools,see the MAX+PLUS IIProgrammable Logic Development System&Software Data Sheet and theQuartus Programmable Logic Development System&Software Data Sheet.,Functional,The MAX 7000 architecture includes the following elements:,Description,Logic array blocks,I,MacrocellsExpander product terms(shareable and parallel)Programmable interconnect arrayI/O control blocks,Altera Corporation,7,MAX 7000 Programmable Logic Device Family Data SheetThe MAX 7000 architecture includes four dedicated inputs that canbe used as general-purpose inputs or as high-speed,global controlsignals(clock,clear,and two output enable signals)for eachmacrocell and I/O pin.Figure 1 shows the architecture of EPM7032,EPM7064,and EPM7096 devices.,Figure 1.EPM7032,EPM7064&EPM7096 Device Block Diagram,INPUT/GLCK1,INPUT/GCLRn,INPUT/OE1,INPUT/OE2,LAB A,LAB B,8 to 16I/O pins,I/OControlBlock,8 to 16,Macrocells1 to 16,36,36,Macrocells17 to 32,8 to 16,I/OControlBlock,8 to 16I/O pins,168 to 16,168 to 16,LAB C,PIA,LAB D,8 to 16I/O pins,I/OControlBlock,8 to 16,Macrocells33 to 48,36,36,Macrocells49 to 64,8 to 16,I/OControlBlock,8 to 16I/O pins,Altera Corporation,168 to 16,168 to 16,8,MAX 7000 Programmable Logic Device Family Data Sheet,Figure 2 shows the architecture of MAX 7000E and MAX 7000S devices.,Figure 2.MAX 7000E&MAX 7000S Device Block Diagram,INPUT/GCLK1,INPUT/OE2/GCLK2,INPUT/OE1,INPUT/GCLRn,6 Output Enables,6 Output Enables,6 to16,LAB A,LAB B,6 to16,6 to 16 I/O Pins,I/OControl,6 to16,Macrocells1 to 16,36,36,Macrocells17 to 32,6 to16,I/OControl,6 to 16 I/O Pins,Block,16,16,Block,6,6 to16,LAB C,6 to16,PIA,6 to16,LAB D,6 to16,6,6 to 16 I/O Pins,I/OControl,6 to16,Macrocells33 to 48,36,36,Macrocells49 to 64,6 to16,I/OControl,6 to 16 I/O Pins,Block,16,16,Block,6,6 to16,6 to16,6,Logic Array BlocksThe MAX 7000 device architecture is based on the linking of high-performance,flexible,logic array modules called logic array blocks(LABs).LABs consist of 16-macrocell arrays,as shown in Figures 1 and 2.Multiple LABs are linked together via the programmable interconnectarray(PIA),a global bus that is fed by all dedicated inputs,I/O pins,andmacrocells.Altera Corporation,I,I,I,2,9,MAX 7000 Programmable Logic Device Family Data SheetEach LAB is fed by the following signals:36 signals from the PIA that are used for general logic inputsGlobal controls that are used for secondary register functionsDirect input paths from I/O pins to the registers that are usedfor fast setup times for MAX 7000E and MAX 7000S devicesMacrocellsThe MAX 7000 macrocell can be individually configured for eithersequential or combinatorial logic operation.The macrocell consistsof three functional blocks:the logic array,the product-term selectmatrix,and the programmable register.The macrocell of EPM7032,EPM7064,and EPM7096 devices is shown in Figure 3.,Figure 3.EPM7032,EPM7064&EPM7096 Device Macrocell,Global,Global,Logic Array,Parallel Logic,Clear,Clocks,FromI/O pin,Expanders(from other,Fast InputSelect,ProgrammableRegister,macrocells)RegisterBypassTo I/OControl,PRND/T Q,Block,Product-TermSelect,Clock/EnableSelect,ENACLRN,MatrixVCCClearSelect,Shared LogicExpanders,to PIA,36 Signals,16 Expander,from PIA,Product Terms,Altera Corporation,2,I,I,MAX 7000 Programmable Logic Device Family Data Sheet,Figure 4 shows a MAX 7000E and MAX 7000S device macrocell.,Figure 4.MAX 7000E&MAX 7000S Device Macrocell,Global,Global,Logic Array,Parallel Logic,Clear,Clocks,fromI/O pin,Expanders(from other,Fast InputSelect,ProgrammableRegister,macrocells)RegisterBypassto I/OControl,PRND/T Q,Block,Product-TermSelect,Clock/EnableSelect,ENACLRN,MatrixVCCClearSelect,Shared LogicExpanders,to PIA,36 Signals,16 Expander,from PIA,Product Terms,Combinatorial logic is implemented in the logic array,which providesfive product terms per macrocell.The product-term select matrix allocatesthese product terms for use as either primary logic inputs(to the OR andXOR gates)to implement combinatorial functions,or as secondary inputsto the macrocells register clear,preset,clock,and clock enable controlfunctions.Two kinds of expander product terms(“expanders”)areavailable to supplement macrocell logic resources:Shareable expanders,which are inverted product terms that are fedback into the logic arrayParallel expanders,which are product terms borrowed from adjacentmacrocellsThe Altera development system automatically optimizes product-termallocation according to the logic requirements of the design.For registered functions,each macrocell flipflop can be individuallyprogrammed to implement D,T,JK,or SR operation with programmableclock control.The flipflop can be bypassed for combinatorial operation.During design entry,the designer specifies the desired flipflop type;theAltera development software then selects the most efficient flipflopoperation for each registered function to optimize resource utilization.,10,Altera Corporation,I,I,I,MAX 7000 Programmable Logic Device Family Data SheetEach programmable register can be clocked in three different modes:By a global clock signal.This mode achieves the fastest clock-to-output performance.By a global clock signal and enabled by an active-high clockenable.This mode provides an enable on each flipflop while stillachieving the fast clock-to-output performance of the globalclock.By an array clock implemented with a product term.In thismode,the flipflop can be clocked by signals from buriedmacrocells or I/O pins.In EPM7032,EPM7064,and EPM7096 devices,the global clock signalis available from a dedic