计算机组成原理课程设计（论文）设计一台嵌入式CISC模型机.doc

计算机组成原理 课程设计(论文)说明书题 目： 设计一台嵌入式CISC模型机系 别： 专 业： 学生姓名： 学 号： 一 CISC模型机数据通路框图总体设计如下嵌入式CISC模型机FCIRALU状态条件寄存器ROMFZ外部时钟DRAC操作控制器和时序产生器复位信号AR具有时间标志的操作控制信号PCR3R2R1R0输出设备输入设备二操作控制器的逻辑框图指令寄存器IR操作码微地址寄存器地址译码控制存储器地址转移逻辑状态条件微命令寄存器P字段操作控制字段微命令信号三模型机的指令系统3.1指令系统76543210I/O指令IN1操作码××RdOUT1操作码Rs××自增指令INC操作码××Rd跳转指令JB操作码××××ADDRJS操作码××××ADDRJMP操作码××××ADDR比较CMP操作码RsRd移动MOV操作码××RdDATAMOV1操作码RsRd测试TEST操作码××Rd3.2本模型机中的指令系统中共有10条基本指令，下表列出了每条指令的格式、汇编符号和指令功能。助记符指令格式功能IN1 Rd0000××Rd将数据存到Rd寄存器OUT1 Rs0011Rs××(Rs)LEDMOV1 Rs,Rd0010RsRdRsRdCMP Rs，Rd0110RsRd(Rs)-(Rd),锁存CY和ZIINC Rd0100××Rd(Rd)+1RdMOV Rd,data0001××RddatadataRdJMP addr0101××××addraddrPCJS addr1 0 00××××addr若为负，则addrPCJB addr1 0 0 1××××addr若小于，则addrPCTest Rd0111××Rd80H-AC，锁存SF说明：对Rs和Rd的规定：Rs Rd选定的寄存器0 0R00 1R11 0R21 1R3模型机规定数据的表示采用定点整数补码表示，单字长为8位，其格式如下：76 5 4 3 2 1 0符号位尾数3.3设计时序产生器电路 T1、T2、T3、T4与CLR、Q之间的关系图QCLRT1T2T3T4一个CPU周期 四微程序流程图00PCARPC+102RD MBUSIR10P(1)IN1TESTJBJSCMPMOVOUT1JMPINCMOV1107191714121816111315RdBUSBUSACRdBUSBUSACPCARPC+1PCARPC+1PCARPC+1RsBUSBUSRdRsBUSBUSACSWBUSBUSRdPCARPC+1RsLED0720050408060300P(3)AC锁存FS00P(2)ROMBUSBUSPCRdBUSBUSDRROMBUSBUSRdAC+1BUSBUSRd00FC=0 或FZ=1 FC=1且FZ=00900000000AC-DR锁存FS和FZ3020ROMBUSBUSPC000000FS=0FS=12808ROMBUSBUSPC五编写汇编语言源程序由给出的题目（范例）和设计的指令系统编写相应的汇编语言源程序。算法思想为：采用R0寄存器存放从开关输入的任意一个整数，R1存放准备参加累加运算的奇数，R2存放累加和，用一个循环程序实现如下：MOV R3,0MOV R2,0MOV R1,5L2:IN1 R0Test R0JS L1L3:INC R2CMP R2,R1JB L2L4:OUT1 R3JMP L4L1: CMP R0,R3 JB L3 MOV1 R0,R3 JMP L3六机器语言源程序根据设计的指令格式，将汇编语言源程序手工转换成机器语言源程序，并将其设计到模型机中的ROM中去。与3.3.8中汇编语言源程序对应的机器语言源程序如下：助记符 地址（十六进制） 机器代码 功能MOV R3,O 00 0001 0011 0R301 0000 000 MOV R2,0 02 0001 0010 0R203 0000 0000 MOV R1,5 04 0001 0001 5R1 05 0000 0101 L2: IN1 R0 06 0000 0000 (SW) R0 Test R0 07 0111 0000 80H-AC JS L1 08 1000 0000 若SF=1 L1PC09 0001 0001 L3: INC R2 0A 0100 0010 (R2)+1R2 CMP R2,R1 0B 0110 1001 (R2)-(R1) JB L2 0C 1001 0000 L2PC OD 0000 0110L4:OUT1 R3 0E 0011 1100 (R3)LEDJMP L4 0F 0101 0000 L4PC 10 0000 1110 L1: CMP R0,R3 11 0110 0011 (R0)-(R3) JB L3 12 1001 0000 L3PC 13 0000 1010 MOV1 R0,R3 14 0010 0011 R0R3 JMP L3 15 0101 0000 L3PC16 0000 1010 七机器语言源程序的功能仿真波形图及结果分析； 输入数值： 85，05，83，87，89 输出结果： 89结果分析： 05是正数，判断为负直接跳出，83<85<87<89所以 89最大，与仿真波形图结果相同八故障现象和故障分析1 问题：为微程序流程图分配首地址时出现错误，导致不能正确译码。 解决方法：进行功能仿真时ADDR进行P（1）测试译码时出现错误的首地址，经过了解P（1）测试原理，重新为微程序流程图分配地址2. 问题： Test指令锁存标志位SF出现错误，无论输入为正为负，SF恒等于0，导致输入负数是不能进行相应的跳转。 解决方法：在进行功能仿真时通过观察ADDR发现错误，查看ALU代码实现中判断输入数值的正负方法有误，经过老师提醒得以解决，解决后的表达式 九心得体会本次课程设计我们要设计一台微程序控制的模型机, 了解了一个比较简单的模型机的实现,完成对计算机组成原理这门课程的综合应用,达到学习本书的作用.作为一个计算机系学生这是必需掌握的。使我们对数据选择器、移位器、加法器、运算器、存储器和微程序控制器，有了比较透彻的认识。由于计算机设计的部件较多、结构原理较复杂，对于我们这样的初设计者来说感到无从下手。在设计过程中，我们从开始的粗略的一个概念，到中间的疑惑与焦虑，到解决了问题的快乐。这对于我们以后工作也有着很大的好处，培养了我们遇到问题，分析问题，解决问题各个方面上的能力。设计结束了，从中我们也学到了不少知识.虽然计算机组成原理的课程设计与学习已经结束,可我们学习之路并没有结束,我们会继续努力学习其相关的知识,以适应社会的发展与需要.这样才能真正成为一名合格的大学生.在这次课程设计的过程，有些很基本的知识出现记混淆的现象，通过查书及询问同学，最终明白了。在此次的设计中，感谢老师对我们的帮助和指导。过程还不够完善，希望老师继续指导。十软件清单1.ALU单元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.all;ENTITY ALU ISPORT( A: IN STD_LOGIC_VECTOR(7 DOWNTO 0); B: IN STD_LOGIC_VECTOR(7 DOWNTO 0); S1,S0: IN STD_LOGIC; BCDOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ; CY,ZI,SF: OUT STD_LOGIC );END ALU;ARCHITECTURE A OF ALU ISSIGNAL AA,BB,TEMP:STD_LOGIC_VECTOR(8 DOWNTO 0);BEGIN PROCESS(S1,S0)BEGIN IF(S1='1' AND S0='1') THEN-TEST BCDOUT<=10000000-A; IF(10000000>=A) THEN SF<='1' ELSE SF<='0' END IF; ELSIF(S1='0' AND S0='1') THEN -CMP(SUB) BCDOUT<=A-B;IF(A<B) THEN CY<='1' ZI<='0' ELSIF(A=B) THEN CY<='0' ZI<='1' ELSE CY<='0' ZI<='0' END IF; ELSIF(S1='1' AND S0='0') THEN -INC AA<='0'&A; TEMP<=A+1; BCDOUT<=TEMP(7 DOWNTO 0); CY<=TEMP(8); IF (TEMP="100000000") THEN ZI<='1' ELSE ZI<='0' END IF;ELSE BCDOUT<="00000000" ; CY<='0' ZI<='0' END IF; END PROCESS;END A; 2.状态条件寄存器单元LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY LS74 IS PORT( LDFR:IN STD_LOGIC; SF,CY,ZI:IN STD_LOGIC; FS,FC,FZ:OUT STD_LOGIC ); END LS74; ARCHITECTURE A OF LS74 IS BEGIN PROCESS(LDFR) BEGIN IF(LDFR'EVENT AND LDFR='1')THEN FC<=CY; FZ<=ZI; FS<=SF; END IF; END PROCESS; END A;3.暂存器单元 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY LS273 IS PORT( D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK:IN STD_LOGIC; O:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END LS273; ARCHITECTURE A OF LS273 IS BEGIN PROCESS(CLK) BEGIN IF(CLK'EVENT AND CLK='1')THEN O<=D; END IF; END PROCESS; END A;4.通用寄存器LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY LS273 IS PORT( D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK:IN STD_LOGIC; O:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END LS273; ARCHITECTURE A OF LS273 IS BEGIN PROCESS(CLK) BEGIN IF(CLK'EVENT AND CLK='1')THEN O<=D; END IF; END PROCESS; END A;5. 1:2分配器单元LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FEN2 IS PORT( WR,LED_B:IN STD_LOGIC; X:IN STD_LOGIC_VECTOR(7 DOWNTO 0); W1,W2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END FEN2; ARCHITECTURE A OF FEN2 IS BEGIN PROCESS(LED_B,WR) BEGIN IF(LED_B='0' AND WR='0')THEN W2<=X; ELSE W1<=X; END IF; END PROCESS; END A;6. 3选1数据选择器单元LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX3 IS PORT( ID:IN STD_LOGIC_VECTOR(7 DOWNTO 0); SW_B,CS:IN STD_LOGIC; N1,N2:IN STD_LOGIC_VECTOR(7 DOWNTO 0); EW:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END MUX3; ARCHITECTURE A OF MUX3 IS BEGIN PROCESS(SW_B,CS) BEGIN IF(SW_B='0')THEN EW<=ID; ELSIF(CS='0')THEN EW<=N2; ELSE EW<=N1; END IF; END PROCESS; END A;7. 5选1数据选择器单元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX5 ISPORT(B,C,D,E,F: IN STD_LOGIC;X1,X2,X3,X4,X5: IN STD_LOGIC_VECTOR(7 DOWNTO 0);W: out STD_LOGIC_VECTOR(7 DOWNTO 0);END MUX5;ARCHITECTURE A OF MUX5 ISSIGNAL SEL: STD_LOGIC_VECTOR(4 DOWNTO 0);BEGIN SEL<=F&E&D&C&B; PROCESS(SEL) BEGIN IF(SEL="11101") THEN -R0_out W<=X1; ELSIF(SEL="11110") THEN -R3_out W<=X5; ELSIF(SEL="11011") THEN -R1_out W<=X2; ELSIF(SEL="10111") THEN -R2-out W<=X3; ELSIF(SEL="01111") THEN -ALU_out W<=X4; ELSE null; END IF; END PROCESS;END A;8. 程序计数器单元LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY PC IS PORT( LOAD,LDPC,CLR:IN STD_LOGIC; D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); O:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END PC; ARCHITECTURE A OF PC IS SIGNAL QOUT:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN PROCESS(LDPC,CLR,LOAD) BEGIN IF(CLR='0')THEN QOUT<="00000000" ELSIF(LDPC'EVENT AND LDPC='1')THEN IF(LOAD='0')THEN QOUT<=D;-BUS->PC ELSE QOUT<=QOUT+1;-PC=PC+1 END IF; END IF; END PROCESS; O<=QOUT; END A;9、地址寄存器10、主存储器单元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ROM16 IS PORT(DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);ADDR:IN STD_LOGIC_VECTOR(7 DOWNTO 0);CS:IN STD_LOGIC);END ROM16;ARCHITECTURE A OF ROM16 ISBEGINDOUT<="00010011" WHEN ADDR="00000000" AND CS='0' ELSE "00000000" WHEN ADDR="00000001" AND CS='0' ELSE "00010010" WHEN ADDR="00000010" AND CS='0' ELSE "00000000" WHEN ADDR="00000011" AND CS='0' ELSE "00010001" WHEN ADDR="00000100" AND CS='0' ELSE "00000101" WHEN ADDR="00000101" AND CS='0' ELSE "00000000" WHEN ADDR="00000110" AND CS='0' ELSE "01110000" WHEN ADDR="00000111" AND CS='0' ELSE "10000000" WHEN ADDR="00001000" AND CS='0' ELSE "00010001" WHEN ADDR="00001001" AND CS='0' ELSE "01000010" WHEN ADDR="00001010" AND CS='0' ELSE "01101001" WHEN ADDR="00001011" AND CS='0' ELSE "10010000" WHEN ADDR="00001100" AND CS='0' ELSE "00000110" WHEN ADDR="00001101" AND CS='0' ELSE "00111100" WHEN ADDR="00001110" AND CS='0' ELSE "01010000" WHEN ADDR="00001111" AND CS='0' ELSE "00001110" WHEN ADDR="00010000" AND CS='0' ELSE "01100011" WHEN ADDR="00010001" AND CS='0' ELSE "10010000" WHEN ADDR="00010010" AND CS='0' ELSE "00001010" WHEN ADDR="00010011" AND CS='0' ELSE "00100011" WHEN ADDR="00010100" AND CS='0' ELSE "01010000" WHEN ADDR="00010101" AND CS='0' ELSE "00001010" WHEN ADDR="00010110" AND CS='0' ELSE "00000000"END A;11、指令寄存器单元12、时序产生器单元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNTER ISPORT( Q,CLR: IN STD_LOGIC; T2,T3,T4: OUT STD_LOGIC );END COUNTER;ARCHITECTURE A OF COUNTER ISSIGNAL X: STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN PROCESS(Q,CLR) BEGIN IF(CLR='0') THEN T2<='0' T3<='0' T4<='0' X<="00" ELSIF(Q'EVENT AND Q='1') THEN X<=X+1; T2<=(NOT X(1) AND X(0); T3<=X(1) AND (NOT X(0); T4<=X(1) AND X(0); END IF; END PROCESS; END A;13、操作控制器单元操作控制器单元内部结构图（1）地址转移逻辑电路LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADDR IS PORT( I7,I6,I5,I4:IN STD_LOGIC; FS,FZ,FC,T4,P1,P2,P3:IN STD_LOGIC; SE6,SE5,SE4,SE3,SE2,SE1:OUT STD_LOGIC);END ADDR;ARCHITECTURE A OF ADDR ISBEGIN SE6<=NOT(NOT FS AND P3 AND T4); SE5<=NOT(NOT FC OR FZ)AND P2 AND T4); SE4<=NOT(I7 AND P1 AND T4); SE3<=NOT(I6 AND P1 AND T4); SE2<=NOT(I5 AND P1 AND T4); SE1<=NOT(I4 AND P1 AND T4);END A;（2）微地址寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MMM IS PORT( SE:IN STD_LOGIC; T2:IN STD_LOGIC; D:IN STD_LOGIC; CLR:IN STD_LOGIC; UA:OUT STD_LOGIC );END MMM;ARCHITECTURE A OF MMM ISBEGIN PROCESS(CLR,SE,T2) BEGIN IF(CLR='0') THEN UA<='0' ELSIF(SE='0')THEN UA<='1' ELSIF(T2'EVENT AND T2='1') THEN UA<=D; END IF; END PROCESS;END A;（3）微地址转换器F1LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY F1 IS PORT( UA5,UA4,UA3,UA2,UA1,UA0: IN STD_LOGIC; D:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);END F1;ARCHITECTURE A OF F1 ISBEGIN D(5)<=UA5; D(4)<=UA4; D(3)<=UA3; D(2)<=UA2; D(1)<=UA1; D(0)<=UA0;END A;（4）控制存储器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CONTROM ISPORT(ADDR: IN STD_LOGIC_VECTOR(5 DOWNTO 0); UA:OUT STD_LOGIC_VECTOR(5 DOWNTO 0); D:OUT STD_LOGIC_VECTOR(19 DOWNTO 0) );END CONTROM;ARCHITECTURE A OF CONTROM ISSIGNAL DATAOUT: STD_LOGIC_VECTOR(25 DOWNTO 0);BEGIN PROCESS(ADDR) BEGIN CASE ADDR IS WHEN "000000" => DATAOUT<="11100110010011110000000010" WHEN "000010" => DATAOUT<="10010110010010110100010000" WHEN "000011" => DATAOUT<="10001110010010110000000000" WHEN "000100" => DATAOUT<="10001111000011110000000000" WHEN "000101" => DATAOUT<="01000110010010110000000000" WHEN "000110" => DATAOUT<="10000010010111110000001001" WHEN "000111" => DATAOUT<="10000111110011111000000000" WHEN "001000" => DATAOUT<="01000110010010110000000000" WHEN "001001" => DATAOUT<="10000110110011111000000000" WHEN "010000" => DATAOUT<="10001110010011010000000000" WHEN "010001" => D